Vertically Spaced Transistor Circuit Structures for SRAM Leakage Control
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Solution Overview
Problem
As semiconductor technology advances, the reduced dimensions of transistors in SRAM cells lead to increased leakage currents and power consumption due to close spacing, which conventional two-dimensional designs struggle to mitigate effectively.
Innovation Solution
The implementation of three-dimensional circuit structures where transistors are laterally adjacent but vertically spaced apart by isolation regions, allowing for electrical isolation without increasing lateral surface area, facilitated by the use of substrates like SOI and buried oxide isolation, and a common gate structure for CMOS inverters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional SRAM cell designs are used with reduced transistor dimensions, then transistor density is improved, but leakage current increases and power consumption increases
Solution Approach 1:
The patent transitions from two-dimensional transistor arrangement to three-dimensional vertical stacking, where transistors are positioned at different height levels above the substrate. This dimensional change allows transistors to be laterally adjacent while vertically separated, achieving high density without the leakage penalties of close lateral spacing in planar designs.
Solution Approach 2:
The patent introduces an isolation region positioned between the channel regions of laterally adjacent transistors. This intermediary structure provides electrical isolation that prevents leakage current while allowing the transistors to maintain close lateral spacing for high density. The isolation region acts as a mediator that enables close packing without the harmful leakage effects.
2Object-generated harmful factors
If transistors are laterally spaced apart to reduce leakage current, then leakage current is inhibited, but surface area increases
Solution Approach 1:
Instead of increasing lateral spacing to reduce leakage, the patent moves the isolation function to the vertical dimension. Transistors can be laterally adjacent (minimizing surface area) while the isolation region provides vertical separation to inhibit leakage current. This resolves the contradiction by addressing leakage through vertical rather than lateral separation.
Solution Approach 2:
The isolation region is positioned beforehand between the channel regions of laterally adjacent transistors to prevent leakage current from developing. This pre-positioned isolation structure cushions against the potential harmful effects of close lateral spacing, allowing transistors to be packed tightly without suffering from leakage issues.
3Length of moving object
If conventional two-dimensional designs are scaled down, then transistor critical dimensions are reduced, but leakage current increases
Solution Approach 1:
The patent escapes the scaling dilemma by moving to three-dimensional vertical stacking. Instead of continuously reducing lateral dimensions (which increases leakage), the design maintains adequate lateral spacing while achieving density through vertical arrangement. The isolation region provides the necessary separation to prevent leakage even as transistors are closely packed laterally.
Solution Approach 2:
The isolation region serves as a mediator that allows transistors to be scaled down and closely packed without suffering from increased leakage. This intermediary structure compensates for the reduced spacing between transistors, enabling continued scaling while maintaining low leakage current through the isolation provided by the region between channel regions.
Data Source
AI summary
Circuit structures, such as inverters and static random access memories, and fabrication methods thereof are presented. The circuit structures include, for instance: a first transistor, the first transistor having a first channel region disposed above an isolation region; and a second transistor, the second transistor having a second channel region, the second channel region being laterally adjacent to the first channel region of the first transistor and vertically spaced apart therefrom by the isolation region thereof. In one embodiment, the first channel region and the isolation region of the first transistor are disposed above a substrate, and the substrate includes the second channel region of the second transistor.