Vertically Stacked SOT-MRAM for Higher Bit Density and Fewer Transistors
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Solution Overview
Problem
Conventional magnetic random-access memory (MRAM) devices face challenges in achieving high bit density and minimizing occupancy area while requiring a large number of transistors for operation, particularly in spin orbit torque magnetic random-access memory (SOT-MRAM) devices.
Innovation Solution
A semiconductor device with a vertically stacked structure comprising a reference layer, free layers, and spin orbit coupling (SOC) layers, where transistors are used to control the connection of these layers to a source line and bit lines, allowing for spin direction determination through resistance value measurements, thereby reducing the number of transistors required for readout operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional SOT-MRAM structure is used, then readout and write operations can be performed, but the occupancy area is large and transistor count is high
Solution Approach 1:
The patent transitions from a planar MRAM structure to a vertically stacked three-dimensional structure. Multiple free layers (first free layer, second free layer) and their corresponding SOC layers are stacked above each other, with each layer pair capable of independent spin direction control. This vertical stacking enables multiple storage bits within a smaller footprint area, directly improving bit density while reducing occupancy area.
2Reliability
If conventional SOT-MRAM structure is used, then data can be stored, but the number of transistors required is large
Solution Approach 1:
The patent combines multiple storage elements (first free layer with first SOC layer, second free layer with second SOC layer) into a single integrated stacked structure. The reference layer serves as a common reference for both free layers, and the tunneling layers are stacked vertically. This merging reduces the need for separate transistor circuits for each storage element, thereby reducing overall transistor count while maintaining data storage capability.
Solution Approach 2:
The reference layer serves multiple functions: it provides a fixed spin direction reference for both the first free layer and the second free layer. The stacked tunneling layers enable independent resistance measurement for each free layer spin direction. This multi-functionality allows the structure to store and read multiple bits using a unified architecture, reducing the need for additional transistors that would be required in conventional separate structures.
3Productivity
If vertically stacked structure is implemented, then bit density increases and occupancy area reduces, but structural complexity increases
Solution Approach 1:
The vertically stacked structure is segmented into distinct functional modules: reference layer, first tunneling layer, first free layer, first SOC layer, second tunneling layer, and second free layer. Each segment has a specific function and can be independently controlled through transistor switching. This segmentation manages structural complexity by organizing the vertical stack into manageable, functionally distinct units while maintaining high bit density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The vertically stacked structure achieves higher bit density with reduced occupancy area and transistor count, outperforming conventional SOT-MRAM by requiring fewer transistors and enabling efficient scaling down.
Implementation Method 1
a first spin orbit coupling (SOC) layer disposed below the first free layer, and configured to control a spin direction recorded in the first free layer by using a current flowing through the first SOC layer
Implementation Method 2
a resistance value between the free layer and the reference layer may be changed based on whether the spin direction recorded in the free layer is the same as the spin direction recorded in the reference layer
Data Source
AI summary
A semiconductor device includes: a reference layer having a fixed spin direction; a metal layer disposed below the reference layer; a first free layer disposed below the metal layer; a first spin orbit coupling (SOC) layer disposed below the first free layer, and configured to control a spin direction recorded in the first free layer by using a current flowing through the first SOC layer; a second free layer disposed below the first SOC layer; and a second SOC layer disposed below the second free layer, and configured to control a spin direction recorded in the second free layer by using a current flowing through the second SOC layer.