Vertically-strained silicon pMTJ switching stability
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Solution Overview
Problem
Current magnetic random access memory (MRAM) technologies face challenges in efficiently switching and maintaining the magnetic orientation of free layers in perpendicular magnetic tunnel junctions (pMTJs) for reliable data storage, particularly in achieving low resistance states and stable non-volatile memory.
Innovation Solution
A method involving the formation of a vertically-strained silicon structure with specific layer configurations, including a groove in a substrate, insulative layers, source and gate terminals, and strained Si drain terminals, to enhance the switching and stability of pMTJs, allowing for efficient magnetization switching and robust data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional MRAM structures are used, then the basic memory function is achieved, but the switching efficiency and magnetic orientation stability are insufficient
Solution Approach 1:
The patent applies parameter changes by introducing vertical strain to the silicon channel, which fundamentally alters the carrier mobility characteristics and effective mass of charge carriers. This strain engineering modifies the band structure parameters to enhance spin-orbit coupling effects, thereby improving both the switching efficiency and magnetic orientation stability simultaneously
Solution Approach 2:
The patent transitions from conventional planar device geometry to a vertically-strained three-dimensional structure. By creating depth-dependent strain fields through the layered configuration (buffer layers, source/drain regions arranged vertically), the invention exploits the third dimension to achieve superior magnetic control and switching performance
2Ease of operation
If higher current is applied to switch MTJ element, then switching between resistance states is achieved, but energy consumption increases
Solution Approach 1:
The vertically-strained silicon structure modifies the electrical parameters (carrier mobility, effective mass) to reduce the current required for switching. The strain-induced band structure changes enable more efficient spin transport, allowing switching at lower current densities and thus reducing energy consumption while maintaining switching capability
3Ease of manufacture
If simple device structure is used, then manufacturing is easier, but magnetic switching control is insufficient
Solution Approach 1:
The device is segmented into distinct functional layers (buffer layers, source line layer, gate terminal, drain terminal) with each layer serving a specific purpose. This segmentation allows independent optimization of each component while maintaining overall manufacturing simplicity through standardized layer-by-layer fabrication processes
Solution Approach 2:
The gate terminal acts as an intermediary component that mediates between the electrical control signals and the magnetic switching action. By introducing this intermediate control element, the device achieves precise magnetic switching control without requiring complex direct magnetic actuation mechanisms
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables reliable switching between low and high resistance states in pMTJs, ensuring stable non-volatile data storage with reduced energy consumption and improved magnetic orientation stability.
Implementation Method 1
vertically-strained silicon device
Implementation Method 2
The switching of the MTJ element between high and low resistance states results from electron spin transfer
Implementation Method 3
The electrical resistance through the MTJ element in a direction perpendicular to the planes of the layers changes with the relative orientations of the magnetizations of the magnetic reference layer and magnetic free layer
Data Source
AI summary
According to one embodiment, a method includes forming a first insulative layer above a bottom surface of a groove and along inner sidewalls thereof, forming a source line layer within the groove of the substrate, forming a first dielectric layer on outer sides of a middle portion of the source line layer, forming a buffer layer on outer sides of the first dielectric layer, forming a gate terminal above the source line layer, forming a gate dielectric layer between the source line layer and the gate terminal and on outer sides of the lower portion of the gate terminal, forming a drain terminal including strained Si on outer sides of the first dielectric layer, and forming a relaxed buffer layer on outer sides of the upper portion of the source line layer and outer sides of the drain terminal, with the gate terminal extending beyond the relaxed buffer layer thickness.