Memory System VFC Circuit for Accurate 3D NAND Fail-Bit Counting
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Solution Overview
Problem
Existing verify fail-bit count (VFC) circuits in 3D NAND memory devices struggle with inaccuracies due to mismatches, leading to inefficiencies in counting fail-bits, which affect the quality and performance of memory devices.
Innovation Solution
A VFC circuit with a comparator unit and trimming unit is introduced to generate an offset signal that compensates for mismatches, adjusting the offset signal based on detected fail-bits to improve accuracy in counting fail-bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a VFC circuit is used to count fail-bits in memory devices, then the quantity of fail-bits can be measured, but mismatches in the circuit lead to counting inaccuracies
Solution Approach 1:
The patent implements a feedback mechanism where the VFC circuit continuously monitors its own counting output and compares it against expected values. When mismatches are detected, the circuit automatically adjusts its internal parameters to correct the counting accuracy, thereby resolving the contradiction between measurement precision and circuit reliability
Solution Approach 2:
The patent changes key circuit parameters dynamically to compensate for mismatches. By adjusting bias currents, threshold voltages, or timing parameters in the VFC circuit, the system maintains accurate fail-bit counting despite variations in manufacturing tolerances or operating conditions
2Measurement precision
If the VFC circuit is designed with high precision components, then counting accuracy improves, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The VFC circuit is designed to self-calibrate and self-correct without requiring complex external calibration equipment or manual adjustment. The circuit automatically detects its own mismatches and adjusts internal parameters to maintain accuracy, thereby achieving high precision without proportionally increasing device complexity
Solution Approach 2:
The patent incorporates preliminary calibration routines that are executed during manufacturing or initialization. These pre-adjustments compensate for systematic mismatches before the device enters normal operation, reducing the need for complex real-time correction mechanisms
3Measurement precision
If the VFC circuit performs real-time mismatch compensation, then counting accuracy improves, but processing time and operational complexity increase
Solution Approach 1:
The mismatch compensation is performed periodically rather than continuously. The VFC circuit executes calibration routines at predetermined intervals or under specific conditions, thereby maintaining high counting accuracy while minimizing the time lost to compensation operations during normal fail-bit counting
Data Source
AI summary
Devices, systems, and methods for counting a quantity of fail-bits in a memory device using a VFC circuit are disclosed. The VFC circuit can be calibrated via an offset adjustment mechanism to compensate an internal mismatch. The VFC circuit can include a processing unit and a circuit coupled to the processing unit. The processing unit can receive a first signal representing a number of detected fail-bits in the memory array, process the first signal and an offset signal, and generate a second signal representing a quantity of fail-bits. The circuit can receive the first and second signals, determine a difference between the quantity of fail-bits represented by the second signal and the number of detected fail-bits represented by the first signal, adjust the offset signal according to the difference, and provide the offset signal to the processing unit.