Vertical Transport FET Airgap Top Spacer Parasitic Capacitance
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Solution Overview
Problem
The increasing density in advanced technology nodes for vertical field effect transistors (VFETs) leads to increased parasitic capacitance between the gate and source/drain epitaxy, which affects device performance.
Innovation Solution
The formation of an airgap between the top spacer and the top source/drain extension regions in the VFET structure reduces parasitic capacitance by creating a vertical airgap top spacer adjacent to the fin and between the top source/drain and the gate electrode, using a combination of nitride and low k dielectric layers and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the density of vertical field effect transistors is increased to improve device integration, then device density is improved, but parasitic capacitance between gate and source/drain epitaxy increases
Solution Approach 1:
The patent extracts the problematic dielectric material between the gate electrode and top source/drain extension regions, replacing it with an airgap. This removal of the dielectric layer eliminates the parasitic capacitance pathway while preserving the structural integrity and electrical functionality of the VFET device.
Solution Approach 2:
The patent changes the physical parameter of the insulating medium from solid dielectric material to air (vacuum), fundamentally altering the capacitance characteristic. By replacing the dielectric with an airgap, the parasitic capacitance is reduced since air has a much lower dielectric constant, thereby resolving the harmful effect while maintaining device density.
2Object-generated harmful factors
If an airgap is formed between the gate electrode and top source/drain extension regions to reduce parasitic capacitance, then parasitic capacitance is reduced, but device structure complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the airgap structure during the fabrication process before final device operation. The dielectric layer is selectively removed and replaced with airgap formation steps integrated into the manufacturing flow, which simplifies the overall process compared to attempting to create airgaps after device assembly.
Solution Approach 2:
The patent uses an intermediary approach by introducing a controlled airgap as a mediating structure between the gate electrode and source/drain regions. This airgap serves as an electrical isolator that reduces parasitic capacitance while maintaining the mechanical and structural framework of the device, thereby managing complexity through a focused structural modification rather than complete redesign.
3Object-generated harmful factors
If precise dimensional control is implemented in the airgap formation process to reduce parasitic capacitance, then parasitic capacitance is reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent replaces traditional mechanical or lithographic dimensional control methods with a chemically-driven self-limiting etching process. The airgap formation utilizes selective chemical reactions that inherently stop at precise depths based on material selectivity and etch kinetics, eliminating the need for complex mechanical positioning or multiple lithography steps to achieve precise dimensional control.
Solution Approach 2:
The manufacturing process employs self-service characteristics through self-aligned and self-limiting etching steps. The airgap formation process automatically controls its own dimensions through material selectivity and etch stop layers, reducing the need for external control mechanisms and simplifying the manufacturing process while achieving the required precision for parasitic capacitance reduction.
Data Source
AI summary
Structures and methods are presented for forming a vertical field effect transistors. The structure generally includes a top source/drain including an L-shaped spacer on sidewalls and a portion of the bottom surface of the top source/drain. At least one airgap top spacer is provided adjacent top sidewalls of the fin and between the top source/drain and the gate electrode.