VFET Backside Contact Layout With 2D Metal Over Diffusion
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Solution Overview
Problem
Existing VFET devices face challenges due to increased area requirements from vertical metal structures and blocked horizontal track routing channels by frontside contacts, which affect device efficiency and layout.
Innovation Solution
The implementation of frontside power contacts, backside contacts, two-dimensional backside contacts, and two-dimensional metal over diffusion (MD) layers, which reduce the area of VFET devices, increase gate density, and minimize metal layer coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vertical metal structures are used to connect backside contacts to frontside, then electrical connection is achieved, but device area increases by one contact poly pitch per structure
Solution Approach 1:
The patent transitions from three-dimensional vertical metal structures to two-dimensional metal-over-diffusion contacts. By eliminating vertical vias and using planar MD layers formed directly over diffusion regions, the connection path changes from vertical to lateral, reducing area occupation while maintaining electrical connectivity between backside and frontside contacts
Solution Approach 2:
The invention extracts and eliminates the vertical metal interconnect structures (vias and vertical metal lines) from the device architecture. By removing these vertical structures and replacing them with planar MD layers, the patent reduces the area overhead associated with each contact while preserving the essential electrical connection function
2Reliability
If frontside input and output contacts use horizontal routing channels, then electrical connection is achieved, but three or more horizontal track routing channels become blocked
Solution Approach 1:
The patent segments the routing function by separating power/contact routing from signal routing. Input and output contacts are routed through dedicated metal layers (M0, M1) that are distinct from the horizontal track routing channels, allowing signal routes to pass underneath or alongside contact structures without blockage, thus maintaining routing channel availability
Solution Approach 2:
The patent uses multiple metal layers stacked vertically to provide alternative routing paths. By distributing contacts and routing across different z-levels (metal layers), the design allows horizontal track routing channels to remain accessible for signal routing while contacts utilize other metal layers for their connections
3Adaptability or versatility
If more vertical metal structures are added to accommodate additional contacts, then contact connectivity increases, but device area and metal layer coupling increase
Solution Approach 1:
The patent merges multiple contact functions into shared metal layers. Power contacts, input contacts, and output contacts all utilize the same metal layers (M0, M1) and routing infrastructure, eliminating the need for separate vertical metal structures for each contact type. This consolidation reduces overall metal layer complexity and coupling while maintaining full connectivity
Solution Approach 2:
The metal layers and routing channels are designed to serve multiple functions simultaneously. The same metal layers that carry contact signals also provide power distribution and signal routing capabilities, reducing the need for dedicated structures for each function and thereby reducing overall device complexity and metal layer coupling
Data Source
AI summary
A device including a first vertical field effect transistor having a first drain/source region and a second drain/source region, and a second vertical field effect transistor having a third drain/source region and a fourth drain/source region. The device including a first power contact situated on a frontside of the device and coupled to the first drain/source region, a second power contact situated on the frontside of the device and coupled to the third drain/source region, and a contact situated on a backside of the device and coupled to the second drain/source region and to the fourth drain/source region.


