VFET Backside Trench Epitaxy for Bottom Source/Drain Formation
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Solution Overview
Problem
Forming bottom source and drain junctions in vertical field-effect transistors (VFETs) is challenging due to control issues during epitaxial growth, which affects device density and performance.
Innovation Solution
The implementation of a backside trench epitaxy region beneath the channel fin, allowing for the formation of a bottom source/drain region using backside interconnect processes, eliminating the need for bottom source/drain contacts and simplifying the manufacturing process while improving device performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional epitaxial growth techniques are used to form bottom source and drain junctions in VFETs, then the manufacturing process becomes complex and difficult to control, but attempting to simplify the process leads to poor device performance and reliability
Solution Approach 1:
The patent inverts the conventional approach by forming the bottom source and drain regions from the backside of the substrate rather than from the front. This backside formation approach simplifies the frontside processing and eliminates complex epitaxial growth control issues while maintaining reliable junction formation, directly resolving the contradiction between manufacturing ease and device reliability
Solution Approach 2:
The patent introduces a sacrificial layer as an intermediary element that enables the backside trench formation process. This sacrificial layer acts as a mediator that facilitates the formation of bottom source/drain regions without directly contacting the final device structure, allowing simplified processing while ensuring reliable junction characteristics
2Productivity
If bottom source and drain junctions are formed using conventional methods, then device density can be maintained, but the manufacturing process becomes complex and difficult to control
Solution Approach 1:
By inverting the formation sequence and creating bottom source/drain regions from the backside, the patent achieves high device density without the complex frontside epitaxial growth processes. This inversion allows parallel processing and simpler control while maintaining the vertical channel structure necessary for high density
Solution Approach 2:
The patent segments the device fabrication into distinct frontside and backside processes. The bottom source/drain formation is separated as a backside operation, allowing independent optimization of each process module. This segmentation reduces overall manufacturing complexity while maintaining high device density through precise spatial control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device density and performance by simplifying the manufacturing process and improving the reliability of VFETs, addressing the challenges of forming bottom source/drain regions through backside interconnect processes.
Implementation Method 1
a bottom source/drain region including a trench epitaxy later located underneath a bottommost surface of the channel fin
Data Source
AI summary
A semiconductor structure with self-aligned backside trench epitaxy includes a channel fin extending vertically from a bottom source/drain region of a field effect transistor. The bottom source/drain region includes a trench epitaxy later located underneath a bottommost surface of the channel fin. A high-k metal gate stack is disposed along sidewalls of the channel fin. The high-k metal gate is separated from the bottom source/drain region by a bottom spacer. A top source/drain region is located above a topmost surface of the channel fin. The top source/drain region is separated from the high-k metal gate by a top spacer. The semiconductor structure further includes a backside metal contact within a backside interlayer dielectric. The backside metal contact is electrically connected to, and vertically aligned with, the bottom source/drain region.