VFET Buried Contact Layout in Fin-to-Fin Space

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Solution Overview

Problem

The challenge in fabricating advanced nonplanar transistors, such as VFETs, is the need for a buried power rail contact that does not consume valuable top-side area while maintaining effective voltage drop and electromigration performance, as scaling down transistors reduces fin length and effective gate length.

Innovation Solution

A buried contact is placed in the fin-to-fin space of VFETs, self-aligned to the fins, which connects the bottom source/drain to a buried power rail, leveraging the area below the active fin without consuming top-side space, thus saving area for longer fins.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a buried power rail contact is placed on the top-side of VFETs, then effective voltage drop and electromigration performance are maintained, but valuable top-side area is consumed

Engineering Contradiction:

Improvevoltage drop and electromigration performanceVSAvoidtop-side area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent moves the buried power rail contact from the top-side (horizontal plane) to the bottom-side of the device (vertical dimension), specifically placing it in the fin-to-fin space at the substrate level. This dimensional relocation allows the contact to maintain electrical connection functionality while eliminating competition for top-side active area, thereby resolving the contradiction between reliability performance and area utilization.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Instead of placing the buried power rail contact on the conventional top-side of the transistor, the patent inverts the approach by positioning it on the bottom-side in the fin-to-fin region. This inversion of the contact location allows the power rail to be accessed from below rather than from above, maintaining its electrical function while freeing up precious top-side area for active device structures.

Inventive Principle:

Principle #13The other way round (Inversion)

2Productivity

If transistor size is scaled down, then device density increases, but fin length and effective gate length are reduced

Engineering Contradiction:

Improvedevice densityVSAvoidfin length and effective gate length

Core Design Contradiction:

ProductivityVSLength of moving object

Solution Approach 1:

By relocating the power rail contact to the bottom-side fin-to-fin space, the patent enables independent optimization of the horizontal dimensions (fin length and gate length) without being constrained by the vertical power delivery path. This dimensional separation allows continued scaling to increase device density while preserving sufficient fin and gate lengths for adequate performance.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11830774B2Buried contact through fin-to-fin space for vertical transport field effect transistor

Publication Date: 2023.11.28 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

Embodiments of the present invention are directed to fabrication methods and resulting structures that provide buried contacts in the fin-to-fin space of vertical transport field effect transistors (VFETs) that connect the bottom S/D of the transistors to a buried power rail. In a non-limiting embodiment of the invention, a buried power rail is encapsulated in a buried oxide layer of a first wafer. First and second semiconductor fins are formed on a second wafer. The first wafer to the second wafer and a surface of the buried power rail in a fin-to-fin space is exposed. A buried via is formed on the exposed surface of the buried power rail. The buried via electrically couples the buried power rail to a bottom source or drain region of the first semiconductor fin.