VFET Cell Width Reduction via Gate Signal Sharing
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Solution Overview
Problem
Designing semiconductor cell architectures for vertical field effect transistors (VFETs) is challenging due to the intrinsic structure where a gate and source/drain vertically overlap, making it difficult to reduce cell width and optimize VFET cell architecture, especially for one-fin VFET devices like one-fin inverters.
Innovation Solution
Implementing a VFET cell architecture that shares gate or source/drain signals between adjacent circuits, allowing for the conversion of X-contacted poly pitch (CPP) circuits to (X−1)-CPP circuits by removing one gate structure and rerouting internal circuitry to share signals, thereby reducing the number of gate structures and optimizing cell width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional gate structures or fin structures are provided next to gate structures where VFETs are formed to allow metal lines to connect contact structures and transmit output signals, then the VFET cell can function properly with signal transmission, but the cell width and area increase
Solution Approach 1:
The patent merges the function of the additional gate structure with the existing gate structure by making them share a common bottom source/drain region. This consolidation allows the gate structures to be closer together or overlap, reducing the overall cell width while maintaining the necessary signal transmission capability through shared electrical connections.
Solution Approach 2:
The patent makes the bottom source/drain region serve multiple functions: it acts as the source/drain for VFETs in one gate structure and simultaneously serves as the source/drain for VFETs in the adjacent gate structure. This multi-functionality eliminates the need for separate bottom source/drain regions, reducing cell area while maintaining proper signal transmission.
2Area of stationary object
If the number of gate structures is reduced to minimize cell width for one-fin VFET devices, then the cell area is reduced, but the ability to connect contact structures to metal lines and transmit output signals is compromised
Solution Approach 1:
The patent combines multiple gate structures into a shared gate structure that serves multiple circuits. By merging the gate structures and their associated bottom source/drain regions, the patent reduces the total number of gate structures needed while maintaining the ability to connect contact structures to metal lines through the shared structure.
Solution Approach 2:
The shared gate structure and its bottom source/drain region perform multiple functions: they provide the necessary gate control for VFETs in different circuits and simultaneously serve as the connection point for metal lines to transmit output signals. This multi-functionality ensures manufacturability and signal transmission are maintained despite reduced gate structure count.
3Area of stationary object
If bottom source/drain regions are merged to reduce the number of gate structures, then the cell width is reduced, but the bottom source/drain regions may become too narrow affecting device performance
Solution Approach 1:
The patent addresses the narrowing issue by extending the merged bottom source/drain region in the vertical direction (along the gate length) rather than maintaining width in the horizontal direction. This dimensional change allows the region to provide sufficient electrical connection area and mechanical support despite the reduced cell width, preventing performance degradation.
Solution Approach 2:
The patent nests multiple VFET devices within the shared gate structure and common bottom source/drain region. By arranging VFETs in a nested or closely integrated configuration, the design maximizes the utilization of the merged bottom source/drain region, ensuring adequate effective width for device performance while achieving overall cell width reduction.
Data Source
AI summary
A vertical field effect transistor (VFET) cell implementing a VFET circuit over a plurality of gate grids includes: a 1st circuit including at least one VFET and provided over at least one gate grid; and a 2nd circuit including at least one VFET and provided over at least one gate grid formed on a left or right side of the 1st circuit, wherein a gate of the VFET of the 1st circuit is configured to share a gate signal or a source/drain signal of the VFET of the 2nd circuit, and the 1st circuit is an (X−1)-contacted poly pitch (CPP) circuit, which is (X−1) CPP wide, converted from an X-CPP circuit which is X CPP wide and performs a same logic function as the (X−1)-CPP circuit, X being an integer greater than 1.