VFET Contact Formation with Titanium Nitride Etch Protection
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Solution Overview
Problem
The formation of contacts in vertical field-effect transistors (VFETs) is challenging due to overlay shift errors that can cause etches to penetrate through protective insulator layers, leading to short-circuits and erosion of source/drain epitaxy, requiring multiple EUV exposure and etching steps and limiting silicide formation to only the uppermost portion of the top source/drain epitaxy.
Innovation Solution
A selective titanium deposition scheme is used to form a titanium liner above the top source/drain regions, followed by a nitridation process to create a titanium nitride protective layer, enabling the formation of contacts during a single EUV exposure and preventing erosion, thus allowing early silicide formation and improved contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional contact formation methods are used in VFETs, then contacts can be formed, but overlay shift errors cause etches to penetrate through protective insulator layers, causing short-circuits and erosion of source/drain epitaxy
Solution Approach 1:
A titanium liner is deposited on the top source/drain regions before contact formation, and a nitride layer is formed over the titanium liner. This preliminary protective layering prevents etch penetration through the insulator layer, avoiding short-circuits and epitaxy erosion while maintaining reliable contact formation
Solution Approach 2:
The titanium liner and nitride layer are deposited beforehand to cushion and protect the underlying source/drain epitaxy and insulator layers from harmful etch attacks, preventing damage before it occurs during the contact formation process
2Reliability
If multiple EUV exposure and etching steps are used to prevent overlay errors, then contact formation reliability improves, but manufacturing complexity and process time increase
Solution Approach 1:
The titanium liner and nitride protective layers are deposited in advance, enabling subsequent contact formation to proceed with simpler, single-mask EUV exposure and etching steps, thereby reducing process complexity while maintaining high reliability
Solution Approach 2:
The titanium liner and nitride layer act as intermediary protective structures that decouple the contact formation process from the underlying sensitive layers, allowing standard single-mask patterning to be used without risking overlay-related damage
3Reliability
If silicide formation is limited to only the uppermost portion of the top source/drain epitaxy, then contact short-circuits are prevented, but contact resistance increases
Solution Approach 1:
The titanium liner serves as an intermediary layer that enables extensive silicide formation across the entire top source/drain region while preventing direct contact between the silicide and underlying sensitive epitaxy, thus achieving low contact resistance without risking short-circuits
Solution Approach 2:
The presence of the titanium liner and nitride layer changes the process parameters, allowing silicide formation to extend deeper and more extensively into the source/drain region than conventional methods permit, thereby reducing contact resistance while maintaining safety margins against short-circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents erosion of the top source/drain epitaxy, enables single-mask EUV exposure for contact patterning, and enhances contact resistance by forming smaller contact openings, allowing for the formation of contacts without short-circuits and improving overall contact quality.
Implementation Method 1
a nitridation process to create a titanium nitride protective layer
Implementation Method 2
the metal gate and the top spacer being in contact with an adjacent first interlevel dielectric layer
Data Source
AI summary
A vertical field effect transistor includes a top source/drain region in contact with a top portion of a channel fin extending perpendicularly from a semiconductor substrate, a bottom source/drain region is disposed above the semiconductor substrate and on opposite sidewalls of a bottom portion of the channel fin, a metal gate surrounding the channel fin is separated from the top source/drain region by a top spacer and from the bottom source/drain region by a bottom spacer, the metal gate and the top spacer are in contact with an adjacent first interlevel dielectric layer. A silicide layer is directly above an uppermost surface of the top source/drain region, and a nitride layer is directly above an uppermost surface of the silicide layer. A top source/drain contact, having a size that is substantially less than a length of the channel fin, extends until an uppermost surface of the nitride layer.