VFET Contact Liner Layout for nFET/pFET Resistance Matching
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Solution Overview
Problem
Existing techniques for forming contact liners in vertical field-effect transistors (VFETs) face challenges in selecting proper silicides and liners for source/drain epitaxial regions, leading to increased costs due to additional lithographic steps and cross-contamination between nFET and pFET devices.
Innovation Solution
The proposed method involves forming a VFET structure with a first VFET having a single liner between the source/drain epi and contact, and a second VFET with two liners, allowing for proper contact liner matching between differing VFET devices, including pFET and nFET devices, while minimizing process steps by using a titanium liner with pFET dopants and optimizing the placement and number of liners to prevent cross-contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If additional lithographic steps are used to select proper silicides and liners for source/drain epitaxial regions, then manufacturing precision is improved, but device complexity and production costs increase
Solution Approach 1:
The patent divides the VFET structures into distinct first and second VFETs with different liner configurations. The first VFET receives a first liner while the second VFET receives a second liner, allowing independent optimization of contact properties for each device type without requiring additional lithographic steps to differentiate the liner selection process.
Solution Approach 2:
The patent applies different liner materials and configurations to different locations (first VFET vs. second VFET) based on their specific electrical requirements. The first liner and second liner are specifically tailored for their respective VFET types, enabling local optimization of contact resistance and electrical properties without affecting other regions.
2Manufacturing precision
If additional lithographic steps are used to form proper contact liners, then contact resistance tuning is improved, but production costs increase
Solution Approach 1:
The patent performs preliminary doping of the liner materials during the liner formation step itself. The first liner is doped with a first dopant and the second liner is doped with a second dopant during their respective deposition processes, eliminating the need for subsequent separate doping steps and reducing overall production costs while achieving the desired contact resistance characteristics.
Solution Approach 2:
The patent changes the electrical parameters of the liners by incorporating different dopants (first dopant for first liner, second dopant for second liner) and varying their thicknesses. This allows precise tuning of contact resistance and electrical properties to match the specific requirements of each VFET type without requiring additional process steps.
3Device complexity
If uniform liner configuration is used for all VFETs, then process simplicity is maintained, but cross-contamination between nFET and pFET devices occurs
Solution Approach 1:
The patent segments the liner formation process into separate treatments for first VFETs and second VFETs. By applying the first liner to first VFETs and the second liner to second VFETs with different configurations and dopants, the process prevents cross-contamination between nFET and pFET devices while maintaining overall process simplicity through concurrent processing.
Solution Approach 2:
The patent implements local quality control by providing different liner materials and dopant configurations specifically where needed (first VFET vs. second VFET regions). This prevents harmful cross-contamination effects by ensuring each VFET type receives the appropriate liner protection and electrical properties without affecting adjacent device types.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables effective silicide formation for nFET and pFET devices without additional lithographic steps, ensuring proper contact liner matching and minimizing cross-contamination, thus improving the tuning of contact resistance and reducing costs.
Implementation Method 1
performing a first ion implantation on the second source/drain epi to form an implanted source/drain epi
Data Source
AI summary
An embodiment of the invention may include a Vertical Field Effect Transistor (VFET) structure, and method of making that structure, having a first VFET and a second VFET. The first VFET may include a single liner between a first source/drain epi and a contact. The second VFET may include two liners between a second source/drain epi and a contact. This may enable proper contact liner matching for differing VFET devices.