VFET Dielectric Protection Layer for ILD Height and Epitaxy Control
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Solution Overview
Problem
The manufacturing process of vertical field effect transistors (VFETs) faces challenges such as oxide loss during the formation of interlayer dielectric (ILD) layers, removal of gate structures, over-etching for top spacers, and forming top epitaxial layers, which reduces ILD bucket volume and causes overgrowth of epitaxial layers, leading to insulation issues and process margin loss.
Innovation Solution
The introduction of an ILD protection layer, specifically a bi-layer or single layer with etch selectivity, is used to prevent height loss of ILD layers, ensuring the top epitaxial layers do not overgrow and maintaining consistent ILD bucket volume, thereby controlling the height and preventing process margin loss by using materials like silicon nitride (SiN) or silicon oxycarbide (SiOC) with appropriate etch selectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If gate structures are removed and top spacers are formed through over-etching, then proper spacing and insulation are achieved, but ILD layer height is reduced and bucket volume is lost
Solution Approach 1:
An ILD protection layer is introduced as an intermediary between the ILD layer and the etching process. This protection layer acts as a sacrificial mediator that absorbs the over-etching damage, preventing direct contact between the etch chemistry and the ILD layer, thereby preserving ILD layer height and volume while still enabling proper spacer formation
Solution Approach 2:
The ILD protection layer is formed preliminarily before the gate removal and spacer formation steps. This preliminary protective action ensures that when subsequent over-etching occurs, the ILD layer is already shielded, preventing height loss and maintaining consistent bucket volume throughout the manufacturing process
2Manufacturing precision
If top epitaxial layers are allowed to grow freely, then source/drain regions are formed, but overgrowth occurs causing insulation issues
Solution Approach 1:
The ILD protection layer serves as a physical barrier and intermediary that prevents direct contact between the top epitaxial layers and the ILD layer. This intermediary structure allows the epitaxial layers to grow to the desired extent for proper source/drain formation while the protection layer maintains the necessary insulation by preventing overgrowth into the ILD region
Solution Approach 2:
The ILD protection layer provides localized protection at the critical interface between the epitaxial growth region and the ILD layer. This local quality enhancement ensures that insulation is maintained precisely where needed (at the ILD interface) while allowing free growth in the source/drain regions, thereby resolving the contradiction between growth freedom and insulation requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents overgrowth of top epitaxial layers, maintains consistent ILD layer height, and ensures proper insulation, thereby simplifying the VFET manufacturing process and improving the formation of VFET devices by maintaining process margins.
Implementation Method 1
an ILD protection layer including a material preventing oxide loss at the ILD layers
Implementation Method 2
an ILD protection layer including a silicon nitride layer is formed on top surfaces of the ILD layers at the sides of the gate structures
Data Source
AI summary
A vertical field effect transistor (VFET) device and a method of manufacturing the same are provided. The method includes: (a) providing an intermediate VFET structure comprising a substrate, and fin structures, gate structures and bottom epitaxial layers on the substrate, the gate structures being formed on the fin structures, respectively, each fin structure comprising a fin and a mask thereon, and the bottom epitaxial layers; (b) filling interlayer dielectric (ILD) layers between and at sides of the gate structures; (c) forming an ILD protection layer on the ILD layers, respectively, the ILD protection layer having upper portions and lower portions, and comprising a material preventing oxide loss at the ILD layers; (d) removing the fin structures, the gate structures and the ILD protection layer above the lower portion of the ILD protection layer; (e) removing the masks of the fin structures and top portions of the gate structures so that top surfaces of the fin structures and top surfaces of the gate structures after the removing are lower than top surfaces of the ILD layers; (f) forming top spacers on the gate structures of which the top portions are removed, and top epitaxial layers on the fin structures of which the masks are removed; and (g) forming a contact structure connected to the top epitaxial layers.