Vertical FET Drive Strength in Double Height Standard Cells
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing standard cells in integrated circuits face challenges in enhancing drive strength of transistors, particularly in vertical field-effect transistor (VFET) devices, where scalability and interconnection complexity are limitations.
Innovation Solution
The design incorporates a double height standard cell structure with multiple VFETs, including P-type and N-type transistors, where channel regions are arranged sequentially and equidistantly, and bottom contacts are strategically placed to improve transistor width and number, thereby increasing drive strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple VFETs are integrated into a standard cell to increase drive strength, then transistor drive strength is improved, but device complexity increases
Solution Approach 1:
The standard cell is segmented into distinct functional regions (first region with first VFET, second region with second VFET, third region with third VFET) separated by cell boundaries. Each VFET is independently structured with its own channel region, gate electrode, and source/drain regions, allowing individual optimization while maintaining overall drive strength enhancement.
Solution Approach 2:
The patent transitions from planar transistor layout to vertical field-effect transistor architecture where channel regions protrude upward from the substrate. This vertical dimension allows multiple VFETs to be stacked and arranged in three-dimensional space within the standard cell, increasing drive strength without proportionally increasing planar footprint or complexity.
2Ease of manufacture
If channel regions are arranged sequentially along the first horizontal direction, then interconnection simplicity is improved, but area utilization decreases
Solution Approach 1:
Channel regions are arranged sequentially along the first horizontal direction with vertical protrusion, utilizing both horizontal and vertical dimensions. This sequential arrangement simplifies interconnection routing along the horizontal axis while the vertical dimension provides additional space for gate electrodes and source/drain structures, improving area utilization.
Solution Approach 2:
Multiple VFETs share common structures including the substrate, isolation layers, and horizontal interconnection routes. The sequential arrangement allows shared power supply lines and signal lines to serve multiple transistors, reducing overall interconnection complexity and area while maintaining manufacturing simplicity.
Data Source
AI summary
Integrated circuit devices including standard cells are provided. The standard cells may a first vertical field effect transistor (VFET) having a first conductivity type, a second VFET having a second conductivity type, and a third VFET having the first conductivity type. The first VFET may include a first channel region protruding from a substrate, and the first channel region has a first length. The second VFET may include a second channel region protruding from the substrate, and the second channel region has a second length. The third VFET may include a third channel region protruding from the substrate. The first channel region, the second channel region, and third channel region may be spaced apart from each other and may be sequentially arranged along a direction, and the second length may be greater than 1.5 times the first length.