Vertical FET Epitaxial Stack Fabrication for Integration Density
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Solution Overview
Problem
The semiconductor industry faces challenges in advancing packaging systems to accommodate denser and smaller electronic components, requiring more advanced technologies to efficiently integrate and connect vertical field-effect transistors (VFETs) within integrated circuits.
Innovation Solution
The method involves forming an epitaxial stack with sacrificial layers and channel layers over a semiconductor substrate, patterning into fin structures, recessing the layers, and replacing dummy spacers with metal gates, while using dual-side power rails and backside connections to optimize VFET layout and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional planar transistors are used, then manufacturing is simpler, but integration density cannot be increased further
Solution Approach 1:
The patent transitions from planar two-dimensional transistor layouts to three-dimensional vertical field-effect transistor (VFET) structures. The VFET includes a channel layer extending vertically from a first surface through a second surface, with source and drain regions positioned at opposite ends of the channel in the vertical direction. This dimensional change enables higher integration density by utilizing the vertical dimension for current transport, allowing more devices to be packed into the same footprint area while maintaining manufacturability through established semiconductor fabrication processes adapted for vertical structures.
2Quantity of substance
If minimum feature size is reduced to increase integration density, then more components can be integrated, but packaging systems become more challenging
Solution Approach 1:
The patent segments the transistor structure into distinct vertical layers including a substrate, sacrificial layers, channel layer, source/drain regions, and gate structures. This segmentation allows each layer to be formed and processed independently using standard semiconductor fabrication techniques, facilitating modular manufacturing and packaging. The vertical segmentation enables denser integration while maintaining compatibility with existing packaging systems by preserving planar processing interfaces.
Solution Approach 2:
The patent changes the geometric parameters of the transistor structure by transitioning from horizontal channel extension to vertical channel extension. The channel layer extends in the vertical direction with a controlled length and cross-sectional area, allowing optimization of electrical parameters such as on-current and threshold voltage while maintaining smaller footprint dimensions. This parameter change enables higher integration density without proportionally increasing packaging complexity.
3Length of moving object
If vertical field-effect transistors are implemented, then cell height scaling is achieved, but parasitic capacitance increases
Solution Approach 1:
The patent applies local quality optimization by positioning the gate structure to wrap around the channel layer at critical locations, creating localized electric field control. The gate is formed with a first portion and a second portion that extend in opposite directions from sidewalls of the channel layer, providing enhanced gate control over the channel while minimizing parasitic capacitance between the gate and source/drain regions. This localized gate configuration reduces overlap capacitance compared to conventional planar structures.
Solution Approach 2:
The patent introduces sacrificial layers as intermediary structures during fabrication. These sacrificial layers are positioned between the substrate and channel layer, and between the channel layer and overlying structures, serving as temporary spacers and isolation elements during the manufacturing process. The sacrificial layers are subsequently removed to create the final vertical structure, enabling precise control of layer spacing and reducing parasitic capacitance in the finished device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables designable current transport directions, reduces poly pitch requirements for logic gates, eliminates the need for isolation breaking, and achieves aggressive cell height scaling with lower parasitic capacitance, enhancing performance and device density.
Implementation Method 1
forming an epitaxial stack with sacrificial layers and channel layers over a semiconductor substrate
Data Source
AI summary
A method includes forming an epitaxial stack including a first sacrificial layer, a channel layer, and a second sacrificial layer over a semiconductor substrate; patterning the epitaxial stack into a fin structure such that opposite first ends of the channel layer are exposed; recessing the opposite first ends of the channel layer; forming first dummy spacers on the recessed opposite first ends of the channel layer; forming an isolation structure in the fin structure; recessing a top surface of the isolation structure to a position lower than a bottom surface of the channel layer, such that opposite second ends of the channel layer are exposed; recessing the opposite second ends of the channel layer; forming second dummy spacers on the recessed opposite second ends of the channel layer; and replacing the first dummy spacers and the second dummy spacers with a metal gate structure.