VFET Fin Segmentation for Epitaxial Growth and Contact Reliability
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Solution Overview
Problem
The challenge in forming vertical field effect transistors (VFETs) lies in the difficulty of epitaxially growing a sufficiently large second source/drain region due to the small surface area of the semiconductor fin, leading to potential contact-related defects such as unlanded contacts and complete silicidation, as the fin thickness decreases with device size scaling.
Innovation Solution
A method is developed to form a semiconductor fin with a thicker top portion to facilitate epitaxial growth of a larger second source/drain region, and then thinning the center portion to achieve optimal VFET performance, ensuring the second source/drain region is sufficiently large to avoid defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device size scaling is performed to increase device density, then device density is improved, but the surface area of the semiconductor fin top becomes too small to facilitate epitaxial growth of a sufficiently large second source/drain region
Solution Approach 1:
The semiconductor fin is segmented into three distinct portions along its length: a first portion at the bottom, a second portion in the middle, and a third portion at the top. This segmentation allows each portion to have different thickness characteristics optimized for its specific function - the third portion maintains greater thickness to provide sufficient surface area for epitaxial growth, while the second portion can be thinned to achieve desired channel characteristics.
Solution Approach 2:
Different regions of the semiconductor fin are given different local properties through selective thinning. The third portion at the top maintains greater thickness to facilitate epitaxial growth of the second source/drain region, while the second portion is thinned to achieve optimal channel region characteristics. This local differentiation resolves the contradiction by allowing the fin to simultaneously provide sufficient surface area and maintain scaled dimensions.
2Manufacturing precision
If the semiconductor fin thickness is reduced to achieve optimal channel dimensions, then VFET performance is improved, but the surface area becomes insufficient for epitaxial growth of the second source/drain region
Solution Approach 1:
The fin is divided into segments with different thickness profiles. The second portion is thinned to achieve precise channel critical dimensions for optimal performance, while the third portion maintains greater thickness to provide adequate surface area for epitaxial growth. This segmentation allows independent optimization of channel dimensions and surface area.
Solution Approach 2:
The selective thinning process is performed as a preliminary action before epitaxial growth. By thinning the second portion while preserving the thickness of the third portion beforehand, the structure is prepared to receive epitaxial material on a sufficiently large surface area, ensuring successful growth of the second source/drain region with appropriate contact formation.
3Productivity
If the second source/drain region is made small due to limited surface area, then device density is improved, but contact-related defects such as unlanded contacts and complete silicidation occur
Solution Approach 1:
The third portion of the fin is maintained with greater thickness to provide sufficient surface area for epitaxial growth of the second source/drain region. This ensures that the contact area is large enough to prevent contact-related defects such as unlanded contacts and complete silicidation, while the overall device density is maintained through the scaled dimensions of other portions of the structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents contact-related defects and enhances the performance of VFETs by ensuring a larger surface area for epitaxial growth, resulting in improved device reliability and functionality.
Implementation Method 1
At least the second portion of the semiconductor fin is thinned relative to the third portion such that the third portion at the top of the semiconductor fin has a first thickness and such that the second portion at a center of the semiconductor fin has a second thickness that is less than the first thickness
Implementation Method 2
semiconductor material can be epitaxially deposited onto the top of the semiconductor fin so as to form a second source/drain region
Data Source
AI summary
Disclosed are embodiments of an improved method for forming a vertical field effect transistor (VFET). In each of the embodiments of the method, a semiconductor fin is formed sufficiently thick (i.e., wide) so that the surface area of the top of the semiconductor fin is sufficiently large to facilitate epitaxial growth thereon of a semiconductor material for a second source/drain region. As a result, the second source/drain region will be sufficiently large to avoid potential contact-related defects (e.g., unlanded contacts, complete silicidation of second source/drain region during contact formation, etc.). Additionally, either before or after this second source/drain region is formed, at least the center portion of the semiconductor fin, which will include the channel region of the VFET, is thinned down to a desired critical dimension for optimal VFET performance. Also disclosed are VFET structure embodiments resulting from this method.