VFET Fin Uniformity via Dielectric Spacer Segmentation
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Solution Overview
Problem
Vertical field effect transistors (VFETs) face challenges in achieving uniform bottom source/drain epitaxial growth and gate length variation due to micro-loading effects during the integration process, leading to non-uniform recess profiles and epitaxial growth variations.
Innovation Solution
The process involves forming semiconductor fins with dielectric spacers, recessing the fins to expose bottom portions, and using a second dielectric inner spacer to seal fin ends before epitaxial growth, which helps in achieving uniform bottom source/drain recess and minimizing the impact of reactive ion etch loading effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fin recess processes are used, then device integration is achieved, but micro-loading effects cause non-uniform recess profiles and gate length variations
Solution Approach 1:
The fin structure is segmented by forming dielectric spacers at different locations (first spacers at upper portions, second spacers at lower portions). This segmentation allows different regions of the fin to be treated differently during recess processes, compensating for micro-loading effects and achieving more uniform recess profiles across the device structure.
Solution Approach 2:
Dielectric spacers are formed in advance before the recess process to pre-establish protective barriers at critical locations. The first spacers are formed on upper fin portions and second spacers on lower portions, creating a preliminary structure that prevents non-uniform etching during subsequent recess operations.
2Manufacturing precision
If reactive ion etching is performed, then fin recess is achieved, but loading effects cause epitaxial growth variations
Solution Approach 1:
Dielectric spacers serve as intermediary protective layers between the reactive ion etch plasma and the fin structures. These spacers (both first spacers at upper portions and second spacers at lower portions) act as mediators that prevent direct plasma interaction with critical fin regions, thereby eliminating loading effects and ensuring uniform epitaxial growth in subsequent processing steps.
Solution Approach 2:
The dielectric spacers are formed in advance to counteract the harmful loading effects before they occur. By pre-placing these protective spacers at strategic locations on the fin structures, the patent prevents the micro-loading effects from manifesting during the reactive ion etching process, thereby maintaining uniform epitaxial growth conditions.
3Productivity
If gate length is reduced for higher density, then device scaling is improved, but control of gate length uniformity becomes difficult
Solution Approach 1:
The gate length definition process is segmented into multiple controlled steps using first and second dielectric spacers formed at different fin portions. This segmentation allows independent control and optimization of gate length dimensions, achieving both reduced gate length for higher density and improved uniformity through precise spacer-based patterning.
Data Source
AI summary
A semiconductor device structure and method for fabricating the same. The semiconductor device structure includes a semiconductor fin and a liner in contact with end portions of the semiconductor fin. A first source/drain contacts the liner and sidewalls of the semiconductor fin. A gate structure is in contact with and surrounds the semiconductor fin. A second source/drain is formed above the first source/drain. The method includes forming, on a substrate, at least one semiconductor fin having a first spacer in contact with an upper portion of the semiconductor fin, and a second spacer in contact with the first spacer and a lower portion of the semiconductor fin. The semiconductor fin is patterned into a plurality of semiconductor fins. A liner is formed on exposed end portions of each semiconductor fin of the plurality of semiconductor fins.