Low-Voltage Flash Memory–VFET Integration for Linearity and Long Retention
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Solution Overview
Problem
Conventional single-device memory elements are either sufficiently linear or have sufficiently long retention times, but not both, leading to the need for hybrid designs that complicate circuitry and require frequent data transfers.
Innovation Solution
A semiconductor structure integrating a low-voltage flash memory with a vertical field effect transistor (VFET) is fabricated, allowing for a simpler circuit design with both long retention times and linearity, reducing device footprint and enabling more devices per chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional single-device memory elements are used, then either linearity or retention time is sufficient, but both cannot be achieved simultaneously
Solution Approach 1:
The patent combines a flash memory cell with a VFET into a single integrated device. The flash memory cell provides long retention time for data storage, while the integrated VFET provides linear operation for analog computing functions. This merging allows the device to simultaneously achieve both linearity and long retention times, eliminating the need for hybrid designs that use separate memory elements and transistors.
2Reliability
If hybrid designs are used to achieve both linearity and long retention times, then both properties can be obtained, but circuit complexity increases and frequent data transfers are required
Solution Approach 1:
The patent merges the flash memory cell and VFET into a single integrated device, eliminating the need for separate memory elements and transistors that would require complex interconnections and frequent data transfers. The unified structure reduces circuit complexity while maintaining both linearity and long retention times.
3Area of stationary object
If conventional memory designs are used, then device footprint is larger, but integration density is reduced
Solution Approach 1:
The patent employs a vertical channel structure for the VFET, where the channel extends vertically through multiple layers rather than horizontally across the substrate. This vertical architecture reduces the horizontal footprint of each device, allowing more devices to be integrated per chip area and thereby increasing integration density.
Data Source
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AI summary
A circuit (400) includes a low-voltage flash memory (200) integrated with a vertical field effect transistor and a non-volatile memory element (100). The low-voltage flash memory is coupled to the non- volatile memory element by the vertical field effect transistor, one or more bit-lines, and one or more word-lines. The low-voltage flash memory may provide a lower significance conductance and the non-volatile memory element may provide a higher significance conductance. The low-voltage flash memory may include a source and a drain. The source may be separated from the drain by an epitaxial channel. The low-voltage flash memory may include a floating gate. The floating gate may be separated from the epitaxial channel by a first dielectric layer. The low-voltage flash memory may include a control gate. The control gate may be separated from the floating gate by a second dielectric layer.