Self-Aligned VFET Gate Extensions for Reduced Fin Pitch
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Solution Overview
Problem
As device density in integrated circuit (IC) designs increases, forming non-planar vertical field effect transistors (VFETs) without violating design rules or causing defects becomes challenging, particularly due to the difficulty in reducing fin pitch below 36 nm without incurring overlay errors during lithographic patterning of extension cut isolation regions.
Innovation Solution
A method of forming self-aligned gates and gate extensions for pairs of VFETs, which wrap around semiconductor fins and fill the space between adjacent ends, eliminating the need for lithographically patterning extension cut isolation regions, thereby enabling reduced fin pitch without defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If lithographic patterning of extension cut isolation regions is used to form VFETs, then device density can be increased, but overlay errors cause defects when fin pitch is reduced below 36 nm
Solution Approach 1:
The gate structure serves dual purposes: it acts as both the transistor gate and as the alignment reference for forming the extension cut isolation regions. The self-aligned process uses the gate's own position to define the isolation region locations, eliminating the need for separate lithographic patterning steps that would introduce overlay errors. This self-service approach allows the fin pitch to be reduced below 36 nm while maintaining manufacturing precision.
2Quantity of substance
If fin pitch is reduced to increase device density, then more devices fit in given area, but defects occur due to overlay errors in lithographic patterning
Solution Approach 1:
The gate structure acts as an intermediary element that mediates between the fin structures and the extension cut isolation regions. By using the gate as the reference for forming isolation regions, the process eliminates direct lithographic patterning of the isolation regions themselves, thereby eliminating the source of overlay errors that would cause defects. This intermediary approach enables reduced fin pitch while maintaining reliability.
3Manufacturing precision
If self-aligned gates and gate extensions are formed simultaneously, then fin pitch can be reduced without overlay errors, but process complexity increases
Solution Approach 1:
The formation of self-aligned gates and gate extensions is merged into a single simultaneous process step. Rather than forming gates first and then separately patterning extension cut isolation regions in subsequent lithographic steps, both structures are formed together using the same lithographic pattern and etch process. This merging reduces the number of process steps and aligns both structures precisely without introducing additional complexity.
Data Source
AI summary
Disclosed is a method of forming an integrated circuit (IC) that incorporates multiple vertical field effect transistors (VFETs) (e.g., in a VFET array). In the method, self-aligned gates for each pair of VFETs and a self-aligned gate extension for contacting those self-aligned gates are essentially simultaneously formed such that the gates wrap around a pair of semiconductor fins, which are in end-to-end alignment, and such that the gate extension fills the space between adjacent ends of those semiconductor fins. By forming self-aligned gates and a self-aligned gate extension for a pair of VFETs, the method avoids the need for lithographically patterning extension cut isolation regions between adjacent pairs of VFETs in a VFET array. Thus, the method enables implementation of VFET array designs with a reduced fin pitch without incurring defects caused, for example, by overlay errors. Also disclosed herein is an IC formed according to the method.