Self-Aligned Gate Extension for Vertical FET Area Reduction
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Solution Overview
Problem
As integrated circuit designs aim to increase device density, forming non-planar FETs like VFETs with reduced fin pitch and gate pitch is challenging without violating design rules or risking defects, and the self-aligned gate structure requires additional gate extensions for contact landing, consuming extra chip area and negating scaling benefits.
Innovation Solution
A semiconductor structure with a combined self-aligned gate/gate extension structure, where a main gate section wraps around the semiconductor fin and an extension section extends along the isolation fin, allowing the gate contact to land on the isolation fin, eliminating the need for additional gate extensions and reducing chip area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the fin pitch is reduced to increase device density, then device density is improved, but gate pitch must also be reduced which increases manufacturing complexity and risk of defects
Solution Approach 1:
The gate structure is merged with the gate extension structure into a single self-aligned gate. The gate is formed to wrap around the semiconductor fin and automatically extend along the isolation fin, combining two previously separate structures into one integrated feature that simplifies manufacturing while maintaining reduced pitch dimensions
Solution Approach 2:
The self-aligned gate structure is formed in advance during the fabrication process such that the gate extension is automatically positioned relative to the gate. This preliminary formation of the combined structure eliminates the need for subsequent separate gate extension formation steps, reducing manufacturing complexity associated with reduced fin and gate pitches
2Length of stationary object
If a self-aligned gate is formed to reduce gate pitch, then gate pitch is reduced, but an additional gate extension is required for contact landing which consumes extra chip area
Solution Approach 1:
The gate and gate extension are merged into a single self-aligned gate structure. The gate material is deposited to wrap around the semiconductor fin and automatically extend along the isolation fin, creating an integrated structure that provides both the gate function and the contact landing surface without requiring additional separate extension structures
Solution Approach 2:
The self-aligned gate structure serves multiple functions simultaneously: it acts as the gate electrode for controlling the channel and also provides the gate extension that serves as the contact landing surface. This multi-functionality eliminates the need for separate gate extension structures, reducing chip area consumption
3Ease of operation
If an additional gate extension is formed to provide contact landing surface, then contact landing is enabled, but chip area is increased which negates scaling benefits
Solution Approach 1:
The gate extension function is merged into the main gate structure. The gate is formed as a continuous structure that wraps around the semiconductor fin and extends along the isolation fin, providing the contact landing surface as an integral part of the gate rather than as a separate additional structure
Solution Approach 2:
The self-aligned gate structure is self-sufficient in providing both gate control and contact landing functions. The gate automatically extends along the isolation fin to provide its own contact landing surface, eliminating the need for external or additional gate extension structures
Data Source
AI summary
Disclosed are embodiments of a semiconductor structure that includes a vertical field effect transistor (VFET). The VFET has a fin-shaped body that includes a semiconductor fin and an isolation fin. The semiconductor fin extends vertically between lower and upper source/drain regions. The isolation fin is adjacent to and in end-to-end alignment with the semiconductor fin. The VFET gate has a main section that wraps around an outer end and opposing sidewalls of the semiconductor fin and an extension section that extends from the main section along at least the opposing sidewalls of a lower portion the isolation fin and, optionally, around an outer end of that lower portion. A gate contact lands on the isolation fin and extends along the opposing sidewalls and, optionally, the outer end of the isolation fin down to the extension section. Also disclosed are method embodiments for forming these structures.