VFET Gate Length Control via Source/Drain Height Variation
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Solution Overview
Problem
Forming vertical field effect transistors (VFETs) with different switching speeds on the same substrate is challenging due to the difficulty in achieving varying threshold voltages, as existing methods struggle to efficiently control gate lengths and resulting device performance.
Innovation Solution
A method is developed to form VFETs with different gate lengths by varying the height of the lower source/drain regions on a semiconductor substrate, ensuring that the top surface of one VFET's source/drain region is below the other's, allowing for distinct gate lengths, threshold voltages, and switching speeds by using sacrificial layers and epitaxial deposition techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If VFETs with different gate lengths are formed on the same substrate, then device performance variability (threshold voltage and switching speed) is improved, but manufacturing complexity increases due to the need for precise height control of lower source/drain regions
Solution Approach 1:
The patent applies preliminary action by forming sacrificial layers at different heights before forming the lower source/drain regions. This pre-established height difference enables subsequent selective epitaxial growth to produce the desired varying gate lengths without requiring complex real-time adjustments during the main fabrication process
Solution Approach 2:
The patent uses sacrificial layers as intermediary structures that facilitate the creation of height differences. These temporary structures enable precise control of lower source/drain region heights during epitaxial growth, and are later removed to reveal the final device structure with varying gate lengths
2Manufacturing precision
If the top surface of lower source/drain region is controlled at different levels, then gate length control is improved, but process precision requirements increase
Solution Approach 1:
The patent applies self-service through self-aligned epitaxial growth, where the epitaxial process automatically stops when it encounters the sidewalls of the semiconductor fins. This self-limiting mechanism enables precise control of lower source/drain region heights and gate lengths without requiring external stopping criteria or complex measurement interventions
Solution Approach 2:
The patent changes the height parameter of sacrificial layers to create different starting levels for lower source/drain region formation. By varying this geometric parameter, the process achieves different gate lengths through controlled epitaxial growth, converting a geometric difference into a functional device parameter
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of VFETs with specific gate lengths, threshold voltages, and switching speeds, enhancing device performance and manufacturing efficiency by allowing multiple VFETs with different characteristics to be produced on the same substrate.
Implementation Method 1
an upper source/drain region that is epitaxially grown on the top surface of the semiconductor fin
Data Source
AI summary
Disclosed is a method of forming a structure with multiple vertical field effect transistors (VFETs). In the method, lower source/drain regions are formed on a substrate such that semiconductor fins extend vertically above the lower source/drain regions. Lower spacers are formed on the lower source/drain regions and positioned laterally adjacent to the semiconductor fins. Gates, having co-planar top surfaces, are formed on the lower spacers and positioned laterally adjacent to the semiconductor fins. However, process steps are performed prior to gate formation to ensure that the top surfaces of the lower source/drain region and lower spacer of a first VFET are below the levels of the top surfaces of the lower source/drain region and lower spacer, respectively, of a second VFET. As a result, the first VFET will have a longer gate, higher threshold voltage and lower switching speed. Also disclosed is the structure formed according to the method.