VFET Gate Length Variation via Segmented Fin Stacking
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Solution Overview
Problem
Vertical field-effect transistor (VFET) devices face gate length variation issues due to fin pitch walking, which results in unwanted fin height variations and subsequent gate length inconsistencies during fabrication.
Innovation Solution
The method involves forming a stack of semiconductor layers with fins extending through the top layer and partway into the bottom layer, creating a staircase structure at the interface to allow for selective thinning of active fin channels, forming sidewall spacers, and constructing gate stacks over bottom spacers to absorb height variations, ensuring uniform gate length and aligned source and drain junctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If fins are patterned in a stack of semiconductor layers, then vertical channel structure is achieved, but fin height variation occurs due to fin pitch walking
Solution Approach 1:
The fin structure is segmented into two distinct parts: the lower fin portion embedded in the first semiconductor layer and the upper fin channel portion in the second semiconductor layer. This segmentation allows independent control and processing of each portion, enabling the lower layer to accommodate pitch walking variations while the upper layer maintains uniform gate length.
Solution Approach 2:
Different regions of the fin structure are given different properties: the lower fin portion in the first semiconductor layer is designed to absorb height variations, while the upper fin channel portion in the second layer is maintained at uniform height. This local differentiation resolves the contradiction by allowing variation absorption in one region while maintaining precision in another.
2Manufacturing precision
If fin pitch walking is reduced, then gate length uniformity improves, but fabrication complexity increases
Solution Approach 1:
The solution moves the problem resolution from the lateral dimension (where pitch walking occurs) to the vertical dimension by using a stacked semiconductor layer structure. The first and second layers are stacked vertically, allowing the lower layer to compensate for lateral pitch variations through vertical height differences, thus solving the uniformity issue without increasing lateral fabrication complexity.
3Manufacturing precision
If active fin channels are selectively thinned to form staircase structure, then sidewall spacers can be formed with uniform thickness, but additional processing steps are required
Solution Approach 1:
The active fin channels are preliminarily thinned to form a staircase structure before sidewall spacer formation. This preliminary action creates a uniform reference surface that enables subsequent sidewall spacers to be deposited with uniform thickness, ensuring precise gate length definition while organizing the complexity into a logical sequence of operations.
Data Source
AI summary
Techniques for reducing gate length variation in VFET devices are provided. In one aspect, a method for forming a VFET device includes: forming a first and a second semiconductor layer as a stack on a substrate; patterning fins in the stack each of which extends completely through the second semiconductor layer and partway into the first semiconductor layer, and wherein portions of the second semiconductor layer in each of the fins include active fin channels; selectively thinning the active fin channels; forming sidewall spacers alongside the active fin channels; forming bottom source and drains at a base of the fins below the sidewall spacers; removing the sidewall spacers; forming bottom spacers on the bottom source and drains; forming gate stacks over the bottom spacers; forming top spacers on the gate stacks; and forming top source and drains on the top spacers. A VFET device is also provided.