Vertical FET Gate Length Variation via Low-Temperature Oxidation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Forming vertical field effect transistors (VFETs) with differing gate lengths on the same wafer is challenging due to their vertical orientation, which complicates the creation of devices with varied gate lengths needed for certain circuit applications.
Innovation Solution
A gas cluster ion beam (GCIB) process is used to selectively recess and oxidize the fins and source/drain regions, allowing for the creation of fins and gates of varying heights and lengths, enabling the fabrication of VFETs with distinct gate lengths on the same wafer without causing dopant diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional high-temperature oxidation processes are used to recess fins, then oxidation can proceed effectively, but dopant diffusion occurs causing device performance degradation
Solution Approach 1:
The patent changes the temperature parameter from conventional high-temperature oxidation to low-temperature oxidation (below 400°C), and introduces a catalyst (nitrogen dioxide or nitrogen trioxide) to enable effective oxidation at the lower temperature. This parameter change allows fin recess to proceed without dopant diffusion while maintaining oxidation effectiveness.
Solution Approach 2:
The patent introduces nitrogen dioxide or nitrogen trioxide as an intermediary substance that acts as a catalyst to enable oxidation at low temperatures. This intermediary allows the oxidation reaction to proceed effectively without requiring high temperatures that would cause dopant diffusion.
2Adaptability or versatility
If VFETs with different gate lengths are formed on the same wafer, then circuit application flexibility is improved, but the vertical orientation makes creating varied gate lengths challenging
Solution Approach 1:
The patent applies selective low-temperature oxidation to specific fin regions to create different fin heights locally on the same wafer. By masking certain areas and oxidizing others, the process creates local variations in fin structure that result in different gate lengths, enabling circuit flexibility without increasing overall fabrication complexity.
Solution Approach 2:
The patent segments the wafer into different regions with different fin heights by using selective oxidation. This segmentation allows different gate length devices to be formed on the same wafer, providing adaptability for various circuit applications while maintaining a unified fabrication process.
3Reliability
If low-temperature oxidation is used to prevent dopant diffusion, then device reliability is maintained, but oxidation effectiveness may be reduced
Solution Approach 1:
The patent changes the oxidation parameters by introducing a catalyst (nitrogen dioxide or nitrogen trioxide) that enables effective oxidation at low temperatures. This parameter change compensates for the reduced thermal energy availability, maintaining oxidation effectiveness while preventing dopant diffusion.
Solution Approach 2:
The catalyst (nitrogen dioxide or nitrogen trioxide) acts as an intermediary that enhances the oxidation reaction rate at low temperatures, ensuring that oxidation effectiveness is maintained despite the lower temperature conditions that prevent dopant diffusion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the precise formation of VFETs with different gate lengths, overcoming the challenges of vertical orientation and achieving effective device fabrication without undesired dopant diffusion, thus supporting advanced CMOS scaling beyond the 5 nanometer node.
Implementation Method 1
forming an oxide (e.g., a GCIB oxide) at a base of the at least one second fin using a low-temperature directional oxidation process (e.g., GCIB oxidation)
Implementation Method 2
A gas cluster ion beam (GCIB) process is used to selectively recess and oxidize the fins and source/drain regions
Data Source
AI summary
Techniques for forming VFETs with differing gate lengths Lg on the same wafer using a gas cluster ion beam (GCIB) process to produce fins of differing heights are provided. In one aspect, a method of forming fins having different heights includes: patterning the fins having a uniform height in a substrate, the fins including at least one first fin and at least one second fin; forming an oxide at a base of the at least one second fin using a low-temperature directional oxidation process (e.g., GCIB oxidation); and removing the oxide from the base of the at least one second fin to reveal the at least one first fin having a height H1 and the at least one second fin having a height H2, wherein H2>H1. VFETs and methods for forming VFETs having different fin heights using this process are also provided.