VFET Gate Liner Cavity Isolation for Lower Parasitic Capacitance
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Solution Overview
Problem
Current manufacturing processes for vertical field-effect transistor (VFET) devices face challenges in improving performance and reliability, particularly in achieving effective isolation and scalability.
Innovation Solution
The method involves forming a preliminary isolation structure with a sacrificial layer and gap capping layer between VFETs, followed by the removal of the sacrificial layer to create a cavity, which enhances isolation and reduces parasitic capacitance by using a gate liner and gap capping layer to enclose the cavity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional isolation structures are used between VFETs, then manufacturing process is simpler, but parasitic capacitance is higher and isolation is ineffective
Solution Approach 1:
The isolation structure is segmented into multiple functional layers: a preliminary isolation structure with sacrificial layer and gap capping layer, followed by a gate liner formed after cavity creation. This segmentation allows each layer to perform its specific function optimally - the preliminary structure provides initial isolation and defines the cavity, while the gate liner provides final parasitic capacitance reduction.
Solution Approach 2:
The preliminary isolation structure is formed before the VFET fabrication process begins, with the sacrificial layer and gap capping layer prepared in advance. This preliminary action establishes the isolation framework and cavity definition early in the process, enabling subsequent steps to proceed efficiently without compromising final isolation effectiveness.
2Productivity
If VFET density is increased to improve scalability, then device integration is improved, but isolation between adjacent devices becomes more difficult
Solution Approach 1:
The isolation approach transitions from planar isolation to three-dimensional cavity isolation. By creating vertical cavities between adjacent VFETs and filling them with dielectric material, the isolation extends into the vertical dimension, enabling effective electrical separation even when devices are densely packed in the horizontal plane.
Solution Approach 2:
The gate liner acts as an intermediary structure between adjacent VFETs, forming a continuous dielectric barrier that mediates the electrical interaction between neighboring devices. This intermediary layer ensures that increased device density does not compromise isolation effectiveness.
3Reliability
If conventional manufacturing processes are used, then process complexity is lower, but performance improvement is limited
Solution Approach 1:
The preliminary isolation structure with sacrificial layer is formed before VFET fabrication, establishing the cavity definition and initial isolation framework. This preliminary action enables subsequent formation of the gate liner and final isolation structure, achieving superior performance through a systematic multi-step process.
Solution Approach 2:
The sacrificial layer is temporarily formed to define the cavity geometry and provide structural support during manufacturing, then selectively removed to create the final isolation cavity. This temporary structure is discarded after serving its purpose, allowing the cavity to be filled with dielectric material for final isolation.
Data Source
AI summary
Vertical field-effect transistor (VFET) devices and methods of forming the same are provided. The methods may include forming a lower structure on a substrate. The lower structure may include first and second VFETs, a preliminary isolation structure between the first and second VFETs, and a gate liner on opposing sides of the preliminary isolation structure and between the preliminary isolation structure and the substrate. Each of the first and second VFETs may include a bottom source/drain region, a channel region and a top source/drain region sequentially stacked, and a gate structure on a side surface of the channel region. The preliminary isolation structure may include a sacrificial layer and a gap capping layer sequentially stacked. The methods may also include forming a top capping layer on the lower structure and then forming a cavity between the first and second VFETs by removing the sacrificial layer.