VFET Gate Electrode Integrity via Replacement Process
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Solution Overview
Problem
Existing manufacturing processes for vertical field-effect transistor (VFET) devices often damage the gate electrode during the formation of the top source/drain region, affecting its properties and reliability.
Innovation Solution
The gate electrode is formed after the top source/drain region, using a replacement gate process through a gate contact opening, ensuring it is not oxidized or damaged by heat, and is enclosed by an insulating layer to protect it during the formation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate electrode is formed before the top source/drain region, then the manufacturing process follows conventional sequence, but the gate electrode is oxidized or damaged by heat during top source/drain formation
Solution Approach 1:
The patent inverts the conventional manufacturing sequence by forming the gate electrode after the top source/drain region instead of before. This reversal prevents the gate electrode from being exposed to oxidation and heat damage during the top source/drain formation process, thereby maintaining gate electrode integrity while still following a systematic manufacturing approach.
Solution Approach 2:
The patent employs preliminary actions by forming placeholder structures (such as sacrificial layers or temporary gates) before the top source/drain region, which are later replaced or removed to create the final gate electrode. This preliminary structuring enables the top source/drain to be formed first while reserving space and alignment for the subsequent gate electrode formation.
2Reliability
If the gate electrode is formed after the top source/drain region, then the gate electrode properties are preserved, but the manufacturing process complexity increases
Solution Approach 1:
The patent implements nesting by placing sacrificial layers or temporary structures within the final gate electrode cavity before top source/drain formation. These nested placeholder structures guide the subsequent gate electrode formation process and are later removed, simplifying the complex sequence of operations by providing clear structural references at each stage.
Solution Approach 2:
The patent introduces intermediary materials such as sacrificial layers, spacer layers, or temporary gates that mediate between the top source/drain formation and the final gate electrode formation. These intermediary structures enable precise positioning and dimensional control of the gate electrode while being removed or transformed in later steps, reducing overall process complexity.
3Productivity
If the gate electrode is exposed during top source/drain formation, then the process follows standard sequencing, but the gate electrode undergoes oxidation and heat damage
Solution Approach 1:
The patent extracts the gate electrode formation step from the conventional sequence and removes it from exposure to harmful conditions by performing it after top source/drain formation. This extraction eliminates the gate electrode's exposure to oxidation and heat damage while maintaining efficient productivity through the inverted sequencing approach.
Solution Approach 2:
The patent creates an inert or protected environment for the gate electrode by forming it after the top source/drain region, when the structure is already enclosed or when subsequent processing occurs in controlled conditions. This inert environment approach prevents oxidation and heat damage while maintaining standard productivity levels.
Data Source
AI summary
Vertical field-effect transistor (VFET) devices and methods of forming VFET devices are provided. The methods may include forming a preliminary VFET on a substrate. The preliminary VFET may include a bottom source/drain region on the substrate, a channel region on the bottom source/drain region, a top source/drain region on the channel region, a patterned sacrificial layer on a side surface of the channel region, and an insulating layer. The top source/drain region and the patterned sacrificial layer may be enclosed by the insulating layer. The methods may also include forming a contact opening extending through the insulating layer and exposing a portion of the patterned sacrificial layer, forming a cavity between the channel region and the insulating layer by removing the patterned sacrificial layer through the contact opening, and forming a gate electrode in the cavity.