Vertical Transistors Merged Active Areas Reduce Resistance

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Solution Overview

Problem

Vertical field-effect transistors (VFETs) face challenges due to separate active areas, leading to higher resistance and increased layout area requirements, which burdens power supplies and consumes precious substrate real estate.

Innovation Solution

The method involves identifying and merging adjacent active area regions with the same electrical potential to form larger active areas, reducing resistance and preserving layout area by prioritizing merges based on performance criteria, and integrating these larger regions into semiconductor device layouts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate active area regions are used for vertical transistors, then device isolation and boundary definition are improved, but resistance increases and layout area is consumed

Engineering Contradiction:

Improvedevice isolationVSAvoidresistance

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

Adjacent active area regions with the same electrical potential are merged into larger continuous regions. This combining approach reduces the number of separate regions and their associated boundaries, thereby reducing resistance while maintaining proper device isolation through the transistor structure itself.

Inventive Principle:

Principle #5Merging (Combining)

2Adaptability or versatility

If separate active area regions are used for vertical transistors, then device boundaries are defined, but layout area increases

Engineering Contradiction:

Improvedevice boundary definitionVSAvoidlayout area

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

Multiple small active area regions are merged into larger continuous regions, reducing the total layout area required. The transistor structures themselves provide the necessary boundary definition, eliminating the need for separate isolation regions between adjacent transistors.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The merged active area regions serve multiple functions simultaneously: they provide continuous electrical pathways to reduce resistance, define device boundaries through the transistor structures, and optimize layout area utilization. This multi-functionality resolves the contradiction between boundary definition and area consumption.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Manufacturing precision

If separate active area regions are used, then critical dimension variation is managed, but power supply burden increases

Engineering Contradiction:

Improvecritical dimension variationVSAvoidpower supply burden

Core Design Contradiction:

Manufacturing precisionVSPower

Solution Approach 1:

Adjacent active area regions connected to the same power supply potential are merged into larger continuous regions. This creates more robust power supply pathways that can handle higher current loads, thereby reducing the burden on power supply structures while maintaining control over critical dimension variations through the manufacturing process.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS9761712B1Vertical transistors with merged active area regions

Publication Date: 2017.09.12 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A method for device layout with vertical transistors includes identifying active area regions in a layout of a semiconductor device with vertical transistors. Sets of adjacent active area regions having a same electrical potential are determined. The sets of adjacent active area regions to be merged are prioritized based upon one or more performance criterion. The sets of adjacent active area regions are merged to form larger active area regions according to a priority.