Super Long Channel VFET Using Semiconductor Pillar
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Solution Overview
Problem
Conventional vertical FET (VFET) architectures face challenges in scaling beyond the 10 nm node due to limitations in gate length manipulations, which restrict the integration of super long channels, and require increases in total layer height, making it difficult to satisfy different contact lengths for source, drain, and gate, while maintaining layer planarity.
Innovation Solution
The method involves forming a pair of semiconductor fins on a substrate with a semiconductor pillar between them, where a bottom doped region extends under all fins and partially under the pillar, and a shared conductive gate is formed over the channel regions, allowing the surface of the pillar to serve as an extended channel region, enabling super long channels without increasing the total layer height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional VFET architecture is used with gate length manipulations, then device density and performance are improved, but channel length is limited and cannot achieve super long channels
Solution Approach 1:
The patent extends the channel from a purely vertical dimension to include a horizontal component by introducing a semiconductor pillar that protrudes from the fin top surface. The gate wraps around both the fin sidewall and the pillar surface, creating a three-dimensional channel path that achieves super long channel length without increasing the vertical layer height, thus maintaining device density while enabling extended channel lengths.
2Length of moving object
If total layer height is increased to achieve super long channels, then channel length is extended, but device complexity and manufacturing difficulty increase
Solution Approach 1:
Instead of increasing the vertical layer height to extend the channel, the patent utilizes the horizontal dimension by forming a semiconductor pillar that protrudes from the fin top surface. The gate is configured to wrap around both the fin sidewall and the pillar surface, creating an extended channel path in three-dimensional space without increasing the vertical footprint, thus avoiding increased device complexity and manufacturing difficulty.
3Ease of manufacture
If conventional VFET architecture is used, then manufacturing process is simpler, but it is difficult to satisfy different contact lengths for source, drain, and gate while maintaining layer planarity
Solution Approach 1:
The patent segments the channel into two distinct parts: a vertical channel portion along the fin sidewall and a horizontal channel portion along the pillar surface. This segmentation allows independent optimization of contact lengths for source, drain, and gate, as each contact can be positioned to access different portions of the segmented channel structure, providing flexibility in satisfying different contact length requirements while maintaining layer planarity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of super long channel VFETs that do not require increased total layer height, allowing for longer channel lengths while maintaining device density and performance, thus overcoming the limitations of conventional VFETs.
Implementation Method 1
A bottom doped region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped
Data Source
AI summary
Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.