VFET and P-I-N Diode Integration on Shared Substrate
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Solution Overview
Problem
As semiconductor devices are scaled down to 7 nm node sizes or less, integrating vertical field effect transistors (VFETs) and P-I-N diodes on the same substrate becomes necessary, but existing technologies face challenges in effectively combining these components without compromising performance.
Innovation Solution
An integrated device is formed by doping a semiconductor substrate to create distinct regions for VFETs and P-I-N diodes, with fin and pillar structures being modified into vertical transistors and diodes respectively, and patterning contacts for electrical coupling, allowing for the simultaneous integration of both components on a shared substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If semiconductor devices are scaled down to 7 nm node sizes or less, then device miniaturization is achieved, but integrating VFETs and P-I-N diodes on the same substrate becomes difficult
Solution Approach 1:
The substrate is divided into distinct first and second substrate regions, with the insulator separating them. VFETs are integrated in the first substrate region while P-I-N diodes are integrated in the second substrate region. This segmentation allows each component type to be optimized independently while maintaining compact integration at 7 nm node scaling.
2Adaptability or versatility
If VFETs and P-I-N diodes are integrated on the same substrate, then device functionality is enhanced, but manufacturing complexity increases
Solution Approach 1:
Different substrate regions are doped with different doping types and concentrations to create optimized local environments for each device type. The first substrate region has doping configured for VFET operation while the second substrate region has doping configured for P-I-N diode operation. This local quality differentiation enables both device types to function optimally on the same substrate without compromising manufacturing feasibility.
3Reliability
If distinct regions for VFETs and P-I-N diodes are created, then device performance is maintained, but substrate area increases
Solution Approach 1:
The insulator is embedded within the substrate to define and separate the first and second substrate regions in a nested configuration. This nesting approach allows distinct functional regions to be packed efficiently within the substrate volume, maintaining device performance through proper separation while minimizing the overall substrate area required for integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the successful integration of VFETs and P-I-N diodes on the same substrate, facilitating continued CMOS scaling beyond 7 nm nodes while maintaining device performance and functionality.
Implementation Method 1
patterning contacts for electrical coupling with the doped upper surface section, at least one of the VFETs and at least one of the P-I-N diodes
Implementation Method 2
P-I-N diodes can also be used as photodetectors or optical receivers. For example, when exposed to light illumination, a current is generated in the P-I-N photodiodes and the magnitude of the current depends on the intensity of the light
Data Source
AI summary
An integrated device is provided. The integrated device includes a substrate having a doped upper surface section and an insulator to define first and second substrate regions on opposite sides thereof. Vertical transistors are operably arranged on the doped upper surface section at the first substrate region. P-I-N diodes are operably arranged on the doped upper surface section at the second substrate region.