VFET Power Line Layering for Flexible 3D Routing Access
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Solution Overview
Problem
Conventional semiconductor techniques face challenges in increasing the flexibility of routing, power input, and pin access for vertical field effect transistors (VFETs) to enhance device density and performance.
Innovation Solution
The semiconductor structure includes a first layer with first power lines, a second layer with VFETs, and a third layer with second power lines, where the second layer is disposed between the first and third layers, allowing VFETs to connect to either the first or second power lines. This configuration enhances routing flexibility and power input accessibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If VFETs use a top-to-bottom drain/source structure, then device density and performance are improved, but routing flexibility and pin access are limited
Solution Approach 1:
The patent transitions from conventional planar FET routing to three-dimensional VFET architecture, where power lines are positioned above and below the VFET layer. This dimensional change enables power input from multiple directions (top and bottom), significantly improving routing flexibility while maintaining the vertical channel structure needed for high device density
Solution Approach 2:
The power delivery network is segmented into multiple independent power lines positioned in different layers (above and below the VFET layer). This segmentation allows different portions of the VFET array to be powered from different directions, enabling flexible routing configurations and improving adaptability for various pin access requirements
2Device complexity
If conventional planar FET routing is used, then routing is simple, but device density and performance are limited
Solution Approach 1:
The patent moves from two-dimensional planar routing to three-dimensional power delivery, with power lines positioned in multiple layers above and below the VFET layer. This dimensional expansion enables higher device density through vertical stacking while maintaining manageable routing complexity through systematic layer organization
Solution Approach 2:
The multi-layer power line structure serves multiple functions: it provides power delivery, enables flexible routing configurations, and supports various pin access patterns. This universal structure can accommodate different device layouts and routing requirements without fundamental redesign, maintaining simplicity while enabling high density
Data Source
AI summary
The present disclosure provides a semiconductor structure. The semiconductor structure includes: a first layer including a plurality of first power lines; a second layer including a plurality of VFETs; a third layer including a plurality of second power line; wherein the second layer is disposed between the first layer and the third layer, a first part of the VETs is connected to the first power lines and a second part of the VETs is connected to the second power lines.