VFET Self-Aligned Contact Structure for Area Reduction
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Solution Overview
Problem
Existing vertical field effect transistors (VFETs) face challenges in reducing device size due to the need for separate areas for gate and power contacts outside the fin structure, leading to space inefficiency in semiconductor cells.
Innovation Solution
The VFET device incorporates a gate contact and/or power contact positioned inside the fin structure, specifically within the H-shaped or line-shaped fin structure, allowing for area gains by eliminating the need for external contact spaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gate contact and power contact are disposed outside the fin structure, then the contacts can be easily formed and accessed, but the semiconductor cell area increases
Solution Approach 1:
The patent merges the gate contact and power contact locations by positioning both contacts inside the fin structure area. The gate contact is formed at a first location within the fin structure, and the power contact is formed at a second location within the same fin structure, eliminating the need for separate external contact areas and reducing overall semiconductor cell area.
Solution Approach 2:
The patent utilizes the vertical dimension and internal spatial arrangement of the fin structure to accommodate multiple contacts. By positioning contacts at different locations within the fin structure's footprint and using selective epitaxial growth to create depth differentiation, the design transforms a two-dimensional contact layout problem into a three-dimensional solution that reduces area while maintaining manufacturability.
2Area of stationary object
If contacts are positioned inside the fin structure, then the semiconductor cell area is reduced, but the manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the gate contact before forming the power contact. The gate contact is established at the first location within the fin structure, and then the power contact is formed at the second location. This sequential approach, combined with selective epitaxial growth, manages the complexity of having multiple internal contacts by establishing them in a controlled sequence rather than simultaneously.
Solution Approach 2:
The patent uses selective epitaxial growth as an intermediary process to manage the complexity of forming multiple contacts within the fin structure. The selective epitaxial growth creates depth differentiation and spatial separation between the gate contact and power contact regions, allowing both contacts to coexist within the fin structure footprint while maintaining their functional independence and simplifying the overall manufacturing process.
Data Source
AI summary
Provided is a structure of a vertical field effect transistor (VFET) device which includes: a fin structure protruding from a substrate, and having an H-shape in a plan view; a gate including a fin sidewall portion formed on sidewalls of the fin structure, and a field gate portion extended from the fin sidewall portion and filling a space inside a lower half of the fin structure; a gate contact landing on the field gate portion at a position inside the lower half of the fin structure; a bottom epitaxial layer comprising a bottom source/drain (S/D) region, and formed below the fin structure; a power contact landing on the bottom epitaxial layer, and configured to receive a power signal; a top S/D region formed above the fin structure; and a top S/D contact landing on the top S/D region.