Self-Aligned RMG Gate Formation for VFET Thermal Protection
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Solution Overview
Problem
Current gate first fabrication techniques for vertical field effect transistors (VFETs) face thermal issues and difficulties in effective area scaling, necessitating a self-aligned replacement metal gate method.
Innovation Solution
A method involving a fin structure with sacrificial materials, where a self-aligned gate is formed by removing portions of sacrificial material, depositing spacers, and applying gate material around the fin, allowing for thermal protection and efficient area scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gate first fabrication technique is used, then gate is patterned early in the process, but thermal issues occur during annealing and effective area scaling becomes difficult
Solution Approach 1:
The gate area is prepared in advance with dummy gate material that occupies the gate space during annealing, preventing thermal damage to the high-k and work function metal layers. The actual gate is then formed later by replacing the dummy gate, ensuring thermal protection is already in place before high-temperature processing.
Solution Approach 2:
A dummy gate structure serves as an intermediary element that protects the sensitive high-k and work function metal layers during thermal processing. This temporary structure absorbs the thermal stress that would otherwise damage the gate materials, allowing proper annealing to occur.
2Productivity
If gate first fabrication technique is used, then gate is formed early, but effective area scaling is compromised
Solution Approach 1:
The gate structure is made dynamic through a two-stage formation process. Initially, a dummy gate occupies the space, allowing source and drain regions to be formed with optimal spacing. Later, the dummy gate is replaced with the actual metal gate, enabling effective area scaling while maintaining fabrication efficiency.
3Temperature
If replacement metal gate is used, then thermal issues are avoided, but self-alignment and gate length definition must be maintained
Solution Approach 1:
The spacer structure serves itself as a self-aligned mask during gate material deposition. The spacer's position is automatically determined by the source and drain regions, ensuring precise gate length definition without requiring additional alignment steps. This self-service mechanism maintains manufacturing precision while enabling thermal protection.
Solution Approach 2:
Traditional mechanical alignment methods are replaced with a self-aligned chemical deposition process. The spacer structure chemically defines the gate boundaries through conformal deposition, eliminating the need for separate alignment operations and ensuring precise gate length while protecting against thermal damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of self-aligned replacement metal gates with desired thermal characteristics and effective area scaling, reducing thermal impact on high-k and work function metal layers, and allowing for varied threshold voltage adjustments without compromising gate length definition.
Implementation Method 1
depositing a spacer above and adjacent the top source or drain
Implementation Method 2
depositing a gate material above the spacer and below the spacer to the sides of the fin
Implementation Method 3
annealing the intermediate structure
Data Source
AI summary
An intermediate semiconductor structure in fabrication includes a silicon semiconductor substrate, a hard mask of silicon nitride (SiN) over the substrate and a sacrificial layer of polysilicon or amorphous silicon over the hard mask. The sacrificial layer is patterned into sidewall spacers, each of the sidewall spacers having vertically tapered inner and outer sidewalls providing a rough triangular shape. The rough triangular sidewall spacers are used as a temporary hard mask to pattern the SiN hard mask.