Vertical Field-Effect Transistor Standard Cell With Shared Source/Drain
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Solution Overview
Problem
Current integrated circuit designs face challenges in achieving high density and efficient interconnections between vertical field-effect transistors (VFETs), which limits their scalability and performance in integrated circuit devices.
Innovation Solution
The design incorporates P-type and N-type VFETs stacked vertically on a substrate with a common gate layer and top contact layer, where the top source/drain regions of both types are electrically connected through a top contact layer, and via contacts are used to connect these regions to conductive lines, allowing for improved interconnections and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If VFETs are stacked vertically to increase density, then device density and scalability are improved, but interconnection complexity and manufacturing difficulty increase
Solution Approach 1:
The patent merges the source/drain regions of adjacent VFETs (both P-type and N-type) into shared common source/drain regions. This merging reduces the number of separate interconnections needed, as multiple transistors can share the same source/drain contacts, thereby reducing interconnection complexity while maintaining high vertical stacking density.
Solution Approach 2:
The common source/drain regions serve multiple functions: they act as source/drain for multiple adjacent VFETs simultaneously, and they provide shared electrical connections that reduce the overall interconnection network. This multi-functionality allows the structure to maintain high density without proportionally increasing interconnection complexity.
2Area of stationary object
If VFETs are stacked vertically to improve scalability, then area efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the vertical stack into distinct functional regions (P-type VFETs, N-type VFETs, common source/drain regions) that can be manufactured using standard planar CMOS processes. This segmentation allows each region to be formed with conventional precision requirements rather than requiring ultra-precise 3D alignment, thereby maintaining area efficiency while managing manufacturing precision requirements.
Solution Approach 2:
The patent transitions from traditional planar side-by-side transistor arrangement to vertical stacking, improving area efficiency. However, it maintains manufacturability by ensuring that the vertical structures can be formed using standard planar processing techniques, effectively using the vertical dimension for density while keeping manufacturing in the well-controlled planar domain.
3Reliability
If P-type and N-type VFETs are spaced apart to reduce interference, then device reliability is improved, but cell area increases
Solution Approach 1:
The patent combines P-type and N-type VFETs into a shared standard cell structure where they share common source/drain regions and are separated by isolation structures. This merging approach allows the transistors to be placed closer together than traditional spaced-apart designs, reducing cell area while maintaining reliability through the isolation structures that prevent interference.
Solution Approach 2:
The patent introduces isolation structures (such as dielectric layers or doping regions) as intermediaries between P-type and N-type VFETs. These intermediary structures electrically isolate the two transistor types, preventing interference and maintaining reliability, while allowing the transistors to be positioned closer together to reduce overall cell area.
Data Source
AI summary
Integrated circuit devices including standard cells are provided. The standard cells may include a P-type vertical field effect transistor (VFET) including a first channel region and a first top source/drain region sequentially stacked on a substrate in a vertical direction, an N-type VFET including a second channel region and a second top source/drain region sequentially stacked on the substrate in the vertical direction, and a top contact layer contacting both the first top source/drain region and the second top source/drain region.