Vertical FET Gate Length Uniformity via SiGe Oxidation
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Solution Overview
Problem
Vertical field-effect transistors (VFETs) face challenges in achieving uniform gate lengths and consistent device performance due to 'fin pitch walking' and iso-dense bias issues in semiconductor fin patterning, leading to variable metal gate recess depth and device performance variability.
Innovation Solution
A method involving the formation of monolithic semiconductor structures with vertical FETs, where a silicon germanium layer is thermally annealed to create condensed silicon germanium regions and oxide structures, allowing for the deposition of a gate dielectric and gate electrode layer, followed by epitaxial growth of top source/drain regions, which helps in achieving uniform gate lengths and improved device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If optical lithography patterning is used for fin formation, then fin structures can be created, but fin pitch walking occurs leading to variable gate length
Solution Approach 1:
A mandrel structure is introduced as an intermediary element to define the gate length. The mandrel is formed before the fins and serves as a reference structure that ensures uniform gate length across all fins, eliminating the pitch walking problem inherent in direct optical lithography patterning.
Solution Approach 2:
The mandrel structure is formed in advance before the fin patterning process. This preliminary structure establishes the gate length dimension that will be replicated across all fins, ensuring consistency before the actual fin formation occurs.
2Volume of moving object
If sidewall image transfer is used for tight fin patterning, then fin pitch can be reduced, but iso-dense bias leads to variable metal gate recess depth
Solution Approach 1:
The mandrel structure serves as an intermediary reference that decouples the fin pitch determination from the gate recess depth determination. This allows tight fin patterning through sidewall image transfer while maintaining uniform gate recess depth by referencing the mandrel rather than relying on iso-dense bias compensation.
3Productivity
If variable metal gate recess depth occurs, then device performance variability increases
Solution Approach 1:
The mandrel structure provides a fixed reference that creates a feedback mechanism for maintaining uniform gate recess depth. The etching process uses the mandrel as a stop or reference point, ensuring that all gates are recessed to the same depth regardless of variations in fin pitch or other process variables.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method results in VFET arrays with uniform gate lengths and improved device performance consistency, along with abrupt top source/drain extension junction profiles, enhancing the overall efficiency and reliability of VFETs.
Implementation Method 1
thermally annealing the first structure subsequent to depositing the oxide layer, thereby causing formation of condensed silicon germanium regions and oxide structures
Implementation Method 2
formation of condensed silicon germanium regions and oxide structures from the silicon germanium portions of the fin structures
Implementation Method 3
a gate dielectric layer is deposited on the semiconductor fin base portions of the fin structures and a gate electrode layer is deposited over the gate dielectric layer
Implementation Method 4
Top source/drain regions are epitaxially formed on the semiconductor fin base portions
Data Source
AI summary
Vertical field-effect transistors are fabricated while controlling gate length by causing enhanced oxidation of silicon germanium regions on parallel semiconductor fin channel regions. Oxidation of the silicon germanium region is accompanied by volume expansion and condensation. Shared or non-shared gate structures are formed on the sidewalls of the semiconductor fin channel regions. A dielectric liner may be incorporated with self-aligned oxide regions to form a composite spacer for providing electrical isolation of the top source/drain regions.