Vertical Field-Effect Transistor Integration via Simultaneous Epitaxy
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Solution Overview
Problem
Conventional vertical field-effect transistor (VFET) integration processes are complex and involve multiple steps, making them inefficient for simplified integration and manufacturing.
Innovation Solution
A method for manufacturing VFETs that involves forming semiconductor layers with varying germanium concentrations, allowing for simultaneous growth of top and bottom source/drain regions and spacers, and self-aligned gate structures with high-k dielectric and gate conductor, reducing parasitic capacitance and increasing source/drain contact volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional VFET integration processes are used, then complete device functionality is achieved, but process complexity increases significantly
Solution Approach 1:
The patent combines the formation of top and bottom source/drain regions into a single epitaxial growth step, and merges spacer formation with the same process step. This consolidation of multiple discrete steps into unified processes directly reduces integration complexity while maintaining complete device functionality.
Solution Approach 2:
The method performs preliminary patterning of the semiconductor layers into fins before source/drain formation, and uses self-alignment principles where the gate structure automatically aligns with the source/drain regions. These preliminary actions simplify subsequent processing steps and reduce the overall number of alignment operations required.
2Manufacturing precision
If multiple discrete steps are used for source/drain and spacer formation, then precise control is achieved, but manufacturing time increases
Solution Approach 1:
The patent merges the formation of top source/drain regions, bottom source/drain regions, and spacers into a single epitaxial growth step. This simultaneous formation maintains precise spatial control through the mask layer geometry while dramatically reducing the number of process steps and increasing manufacturing throughput.
Solution Approach 2:
The mask layer serves as an intermediary that enables simultaneous formation of multiple structures. By controlling the mask layer's position and geometry, the process achieves precise control over source/drain region formation while enabling parallel processing that improves manufacturing efficiency.
3Ease of manufacture
If horizontal device architecture is used, then simple manufacturing is achieved, but short-channel control degrades
Solution Approach 1:
The patent transitions from horizontal current flow architecture to vertical current flow architecture. This dimensional change enables the gate to effectively control the channel in the vertical direction, improving short-channel control while maintaining manufacturing feasibility through adapted epitaxial growth and patterning processes.
4Productivity
If gate length is reduced, then device density increases, but contact gate pitch space decreases
Solution Approach 1:
By transitioning to vertical current flow, the gate length can be reduced in the vertical direction without proportionally reducing the horizontal contact gate pitch. This dimensional separation allows higher device density to be achieved while preserving sufficient space for contacts and interconnect structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the integration process, reduces parasitic capacitance, and lowers resistance by enabling simultaneous formation of source/drain regions and self-aligned gate structures, thereby improving the efficiency and performance of VFETs.
Implementation Method 1
forming a first semiconductor layer on a semiconductor substrate, forming a second semiconductor layer including a first concentration of germanium on the first semiconductor layer, and forming a third semiconductor layer on the second semiconductor layer. The first and third semiconductor layers each have a concentration of germanium, which is greater than the first concentration of germanium.
Implementation Method 2
a bottom source/drain region and a top source/drain region are simultaneously grown from the first semiconductor layer and the third semiconductor layer, respectively
Data Source
AI summary
A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate, forming a second semiconductor layer including a first concentration of germanium on the first semiconductor layer, and forming a third semiconductor layer on the second semiconductor layer. The first and third semiconductor layers each have a concentration of germanium, which is greater than the first concentration of germanium. The first, second and third semiconductor layers are patterned into at least one fin. The method further includes covering the second semiconductor layer with a mask layer. In the method, a bottom source/drain region and a top source/drain region are simultaneously grown from the first semiconductor layer and the third semiconductor layer, respectively. The mask layer is removed from the second semiconductor layer, and a gate structure is formed on and around the second semiconductor layer.