VFET STI Structure Recess Delay for Isolation
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Solution Overview
Problem
The manufacturing of vertical field effect transistors (VFETs) faces challenges in isolating fin structures effectively, leading to increased capacitance and reduced AC performance due to short circuits and unnecessary capacitance from residue gate structures in shallow trench isolation (STI) processes.
Innovation Solution
The implementation of a recess delay structure in the STI dielectric allows for controlled etching, preventing over-recess and residue formation, thereby maintaining the STI structure above the top surface of the doped layer and ensuring proper gate formation without short circuits, using materials like SiN for etch selectivity and delay in etching at the shallow trench position.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional STI process is used to isolate fin structures, then isolation is achieved, but over-recess occurs and residue gate structures form causing short circuits and increased capacitance
Solution Approach 1:
A recess delay structure is formed at the shallow trench position before the etching process. This preliminary structure prevents over-recess of the STI dielectric by controlling the etching depth, ensuring the STI structure remains at or above the top surface of the doped layer. The recess delay structure is removed after serving its protective function, leaving a precisely positioned STI structure without residue gate structure short circuits.
Solution Approach 2:
The recess delay structure acts as an intermediary element during the STI formation process. It temporarily occupies the shallow trench position to prevent the etching tool from removing too much STI dielectric. This intermediary structure enables precise control of the STI depth while allowing the rest of the process to proceed normally.
2Reliability
If deeper etching is performed to improve isolation, then isolation between fin structures is enhanced, but capacitance increases and AC performance deteriorates
Solution Approach 1:
The recess delay structure is formed in advance at the shallow trench position to prevent over-recess during the etching process. By controlling the etching depth to stop at or above the doped layer top surface, the invention achieves sufficient isolation between fin structures while preventing the formation of residue gate structures that would increase capacitance and degrade AC performance.
3Ease of manufacture
If standard etching process is used, then manufacturing simplicity is maintained, but residue formation occurs causing short circuits
Solution Approach 1:
The recess delay structure is formed as an additional preliminary step before the standard etching process. This simple addition prevents residue gate structure formation and short circuits without significantly complicating the manufacturing process. The delay structure is removed after serving its protective function, leaving a clean STI structure.
Solution Approach 2:
The recess delay structure serves as a temporary intermediary that protects against short circuits during the etching process. It mediates between the etching tool and the STI dielectric, preventing harmful over-recess while allowing the standard etching process to continue. After fulfillment of its protective role, it is removed leaving no residue.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents short circuits and reduces unnecessary capacitance, enhancing the AC performance and productivity of VFET devices by ensuring accurate isolation and gate structure formation without residue issues.
Implementation Method 1
using materials like SiN for etch selectivity and delay in etching at the shallow trench position
Data Source
AI summary
A method for manufacturing a vertical field effect transistor (VFET) device may include: providing an intermediate VFET structure including a substrate, a plurality of fin structures formed thereon, and a doped layer formed on the substrate between the fin structures, the doped layer comprising a bottom source/drain (S/D) region; forming a shallow trench through the doped layer and the substrate below a top surface of the substrate and between the fin structures, to isolate the fin structures from each other; filling the shallow trench and a space between the fin structures with an insulating material; etching the insulating material filled between the fin structures above a level of a top surface of the doped layer, except in the shallow trench, such that a shallow trench isolation (STI) structure having a top surface to be at or above a level of the top surface of the doped layer is formed in the shallow trench; forming a plurality of gate structures on the fin structures, respectively; and forming a top S/D region above the fin structures.