VFET Gate Length Variation via Top Source Drain Positioning
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Solution Overview
Problem
Existing techniques face challenges in forming vertical field effect transistors (VFETs) with differing gate lengths on the same chip due to alignment issues with the physical gate, making it difficult to reduce off-current leakage and power consumption effectively.
Innovation Solution
A method involving patterning fins in a substrate, forming bottom and top spacers, and varying the positioning of top source and drains relative to the vertical fin channels to achieve different effective gate lengths for VFET devices, allowing for both 'wimpy' and nominal VFETs to be fabricated on the same chip with varying gate lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the gate length is increased to reduce off-current leakage and power consumption, then power consumption is reduced, but it becomes difficult to implement FETs of differing lengths in VFET architecture due to alignment challenges
Solution Approach 1:
The patent segments the gate structure into multiple sections with different lengths along the channel. Specifically, the gate is divided into a first section and a second section, where the first section has a different length than the second section. This segmentation allows different portions of the transistor to have different effective gate lengths, enabling optimization for both power consumption and manufacturing alignment.
Solution Approach 2:
The patent applies local quality by creating regions with different gate lengths within the same transistor structure. The first section of the gate has a specific length optimized for certain performance characteristics, while the second section has a different length optimized for other characteristics. This local differentiation allows the transistor to exhibit different electrical properties in different regions, addressing both power consumption reduction and alignment feasibility.
2Loss of energy
If FETs of differing lengths are implemented to optimize power consumption on non-critical paths, then power consumption is reduced, but alignment challenges make it difficult to form VFETs with differing gate lengths on the same chip
Solution Approach 1:
The gate is segmented into distinct sections with different lengths, where each section can be independently optimized. The first section extends along a first portion of the channel while the second section extends along a second portion, allowing precise control over the effective gate length in each region without requiring complex alignment of entirely different gate structures.
Solution Approach 2:
The multi-section gate structure serves multiple functions simultaneously: it provides different effective gate lengths for power optimization, maintains a unified vertical fin channel architecture for manufacturing consistency, and enables both 'wimpy' transistors (with shorter effective gate length) and nominal transistors (with longer effective gate length) to be formed on the same chip using the same fabrication process.
Data Source
AI summary
Techniques for forming VFETs with differing gate lengths are provided. In one aspect, a method for forming a VFET device includes: patterning fins in a substrate, wherein at least one of the fins includes a vertical fin channel of a FET1 and at least another one of the fins includes a vertical fin channel of a FET2; forming a bottom source and drain; forming bottom spacers on the bottom source and drain; forming gates surrounding the vertical fin channel of the FET1 and FET2; forming top spacers on the gate; and forming top source and drains at the tops of the fins by varying a positioning of the top source and drains relative to at least one of the vertical fin channel of the FET1 and the FET2 such that the FET1/FET2 have an effective gate length Lgate1/Lgate2, wherein Lgate1>Lgate2. A VFET device is also provided.