V-FinFET Vertical Fin Transistor Leakage Current Control
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Solution Overview
Problem
As transistors shrink, they experience increased leakage current, leading to battery drainage and overheating in semiconductor chips, which existing transistor structures have not adequately addressed.
Innovation Solution
A vertical fin field effect transistor (V-FinFET) design is implemented, featuring a fin structure with a stacked gate oxide layer and gate electrodes, along with spacers, to reduce leakage current by controlling the gate length and preventing electrical shorts between the gate electrodes and source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is reduced to increase integration density, then productivity is improved, but leakage current increases causing energy loss and heat generation
Solution Approach 1:
The patent transitions from planar 2D transistor structures to vertical 3D FinFET structures. The fin structure extends vertically from the substrate, creating a three-dimensional channel that increases the effective channel area and integration density while maintaining better gate control over the leakage current through the vertical fin geometry.
Solution Approach 2:
The patent implements a stacked gate structure where multiple gate electrodes are vertically stacked around the fin channel. This nested arrangement allows multiple gate layers to control the same channel region, providing enhanced electrostatic control over the leakage current while maintaining a compact footprint that improves integration density.
2Productivity
If gate length is reduced to improve device scaling, then productivity is improved, but manufacturing precision requirements increase due to spacer formation constraints
Solution Approach 1:
The patent divides the gate structure into multiple discrete gate electrodes stacked vertically, with spacers formed between them. This segmentation allows the gate length to be defined by the fin dimensions rather than requiring precise single-step spacer formation, enabling better device scaling while reducing manufacturing precision constraints.
Solution Approach 2:
The patent forms the fin structure and spacers before completing the gate electrode formation. This preliminary action establishes the gate length dimensions early in the process through the fin geometry and spacer thickness, allowing subsequent gate electrodes to be formed without requiring ultra-precise alignment, thus improving device scaling while managing manufacturing precision requirements.
3Reliability
If vertical fin structure is implemented to reduce leakage current, then reliability is improved, but device complexity increases due to additional spacers and stacked gates
Solution Approach 1:
The patent combines multiple gate electrodes into a vertically stacked configuration that functions as an integrated gate system. The spacers between gate electrodes serve dual purposes: defining gate lengths and providing electrical isolation. This merging of functions reduces the need for separate structures, improving leakage control while managing overall device complexity.
Solution Approach 2:
The spacers in the vertical FinFET structure serve multiple functions: they define the gate length dimensions, provide electrical isolation between stacked gate electrodes, and establish alignment references for subsequent processing steps. This multi-functionality reduces the need for additional dedicated structures, improving reliability while controlling device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The V-FinFET design effectively reduces leakage current, thereby improving the efficiency and reliability of semiconductor devices by minimizing battery drainage and heat generation.
Implementation Method 1
The fin structure is epitaxially grown from the lower S/D
Data Source
AI summary
A vertical fin field effect transistor (V-FinFET) is provided as follows. A substrate has a lower source/drain (S/D). A fin structure extends vertically from an upper surface of the lower S/D. The fin structure includes a sidewall having an upper sidewall portion, a lower sidewall portion and a center sidewall portion positioned therebetween. An upper S/D is disposed on an upper surface of the fin structure. An upper spacer is disposed on the upper sidewall portion. A lower spacer is disposed on the lower sidewall portion. A stacked structure including a gate oxide layer and a first gate electrode is disposed on an upper surface of the lower spacer, the center sidewall portion and a lower surface of the upper spacer. A second gate electrode is disposed on the first gate electrode.