Variable Gain Amplifier Source Capacitor Layout for Supply Noise Rejection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Variable gain amplifiers (VGAs) face challenges in reducing power supply noise propagation into the signal path, requiring large integrated circuit area and excessive wiring for capacitors, which leads to unwanted peaking in gain-frequency responses due to low capacitance density and parasitic reactance.
Innovation Solution
The solution involves coupling variable capacitors between the power supply rail and the sources of the FETs, allowing noise cancellation across the gate-to-source voltage and increasing capacitance density, thereby reducing IC area and parasitic reactance, and using a previous stage circuit to generate differential signals that include noise from the power supply rail, which is then coupled to the capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If variable capacitors are coupled between sources of input differential FETs, then power supply noise is reduced, but integrated circuit area increases and wiring parasitic increases
Solution Approach 1:
The patent couples capacitors from the FET sources to a third voltage rail instead of between the two existing voltage rails. This dimensional change in circuit topology allows noise rejection without requiring large capacitor values, thereby reducing IC area while maintaining power supply noise rejection.
Solution Approach 2:
The patent applies different capacitance values to different sides of the differential pair (C1 for first FET, C2 for second FET) to optimize local noise rejection at each node. This localized approach allows tailored noise cancellation while minimizing overall capacitor size and IC area.
2Object-affected harmful factors
If variable capacitors are coupled between sources of input differential FETs, then power supply noise is reduced, but wiring parasitic increases causing unwanted peaking
Solution Approach 1:
By introducing a third voltage rail as a reference point for capacitor coupling, the patent reduces the voltage swing across capacitors and minimizes wiring length requirements. This dimensional change in circuit architecture reduces wiring parasitic inductance and resistance that would otherwise cause unwanted peaking in the gain-frequency response.
3Object-affected harmful factors
If capacitor value is increased to reduce noise, then noise rejection improves, but capacitance density decreases requiring more area
Solution Approach 1:
The patent achieves effective noise rejection by coupling capacitors to a third voltage rail, which allows using smaller capacitor values compared to traditional two-rail configurations. This dimensional change in circuit topology improves capacitance density while maintaining power supply noise rejection performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces power supply noise propagation, decreases IC area and wiring parasitic effects, and results in a gain-frequency response with less unwanted peaking at high frequencies while maintaining a higher gain profile for high frequency components.
Implementation Method 1
a first capacitor coupled between a third voltage rail and the first source of the first FET; and a second capacitor coupled between the third voltage rail and the second source of the second FET
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
A voltage gain amplifier (VGA) configured to have reduced supply noise. The VGA includes first resistor, first FET, and a first current-source coupled between first and second voltage rails. The VGA includes second resistor, second FET, and second current-source coupled between the voltage rails. A variable resistor is coupled between the respective sources of the first and second FETs. Variable capacitors are coupled between the first or a third voltage rail and the sources of the first and second input FETs, respectively. If capacitors are coupled to the first voltage rail, noise cancellation occurs across the gate-to-source voltages of the FETs if an input differential signal applied to the gates of the FETs is derived from a supply voltage at the first voltage rail. If capacitors are coupled to the third rail, supply noise is reduced if the supply voltage at the third rail is generated by a cleaner regulator.