VGAA Transistor Shared Plate Connection Structure for SOI Substrates
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Solution Overview
Problem
Current connection structures for Vertical Gate All Around (VGAA) devices on semiconductor-on-insulator (SOI) substrates face challenges in scaling integrated circuits due to limitations in layout and connection efficiency, which affect the performance and density of integrated circuits.
Innovation Solution
The proposed solution involves a connection structure where NMOS and PMOS VGAA transistors share a top plate or a bottom plate, allowing for a reduced surface area footprint and improved routing efficiency, utilizing a semiconductor-on-insulator (SOI) substrate with oxide diffusion layers and high-K gate dielectric materials to enhance the connection and performance of VGAA nanowire devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional connection structures are used for VGAA devices, then routing connections can be established, but the surface area footprint is large and scaling is limited
Solution Approach 1:
The patent merges the source and drain regions of adjacent transistors into shared common regions. Specifically, the source region of one transistor serves as the drain region of an adjacent transistor, creating shared source/drain regions that reduce the overall surface area footprint and improve routing efficiency by eliminating redundant connection structures
Solution Approach 2:
The common source/drain regions serve multiple functions simultaneously: they act as the source for one transistor, the drain for another transistor, and provide shared electrical connections for multiple devices. This multi-functionality reduces the number of separate connection structures needed, thereby reducing surface area while improving scaling
2Productivity
If separate source and drain regions are used for each transistor, then device functionality is maintained, but layout efficiency and density are reduced
Solution Approach 1:
Adjacent transistors share common source and drain regions, merging what would traditionally be separate regions into unified structures. This reduces layout complexity by minimizing the number of discrete connection elements while maintaining full device functionality
Solution Approach 2:
The patent transitions from planar 2D transistor layouts to vertical 3D VGAA structures with gates wrapping around channels in all directions. This dimensional change allows for more efficient space utilization and simpler connection structures by exploiting the vertical dimension rather than requiring extensive lateral routing
Data Source
AI summary
A vertical gate all around (VGAA) nanowire device circuit routing structure is disclosed. The circuit routing structure comprises a plurality of VGAA nanowire devices including a NMOS and a PMOS device. The devices are formed on a semiconductor-on-insulator substrate. Each device comprises a bottom plate and a top plate wherein one of the bottom and top plates serves as a drain node and the other serves as a source node. Each device further comprises a gate layer. The gate layer fully surrounds a vertical channel in the device. In one example, a CMOS circuit is formed with an oxide (OD) block layer that serves as a common bottom plate for the NMOS and PMOS devices. In another example, a CMOS circuit is formed with a top plate that serves as a common top plate for the NMOS device and the PMOS devices. In another example, a SRAM circuit is formed.