VGAA Test Array Segmentation for Accurate Transistor Measurement
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Solution Overview
Problem
The performance of Vertical Gate-All-Around (VGAA) transistors is adversely affected by the high resistance of bit lines and word lines during testing, leading to inaccurate test results.
Innovation Solution
A test structure is designed with a first area and a second area, where word lines and bit lines in the first area are disconnected from those in the second area, forming a small-sized test array with VGAA transistors in the first area, allowing the device to be tested to connect through shorter lines, reducing the influence of high resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional test structure with continuous word lines and bit lines is used, then the test structure is simple and easy to manufacture, but the high resistance of bit lines and word lines significantly affects the performance measurement of VGAA transistors, leading to inaccurate test results
Solution Approach 1:
The test structure is divided into a first area containing a test array of VGAA transistors and a second area, with disconnection structures between the two areas. Word lines and bit lines in the first area are disconnected from those in the second area, creating isolated test regions. This segmentation allows independent testing of VGAA transistors without interference from the resistance of extended interconnect lines, thereby improving measurement precision while maintaining reasonable structural complexity.
2Measurement precision
If the test array size is increased to improve statistical significance, then more transistors can be tested simultaneously, but the influence of bit line and word line resistance increases, reducing test accuracy
Solution Approach 1:
By segmenting the test structure into discrete areas with disconnected interconnects, the patent enables testing of multiple transistors in the first area while isolating them from the resistance effects of the second area. This allows for scalable test arrays that maintain measurement precision even as the number of transistors tested increases.
Solution Approach 2:
The patent creates locally optimized test regions where the interconnect structure is specifically designed for low-resistance connections within the first area, while the disconnection from the second area prevents propagation of resistance effects. This local quality optimization ensures high measurement precision for each transistor tested, regardless of the total number of transistors in the structure.
Data Source
AI summary
A test structure includes a plurality of word lines and a plurality of bit lines. A vertical gate-all-around (VGAA) transistor is formed at the intersection of each word line and each bit line. The test structure includes a first area and a second area. The second area is arranged outside the first area, the word lines in the first area and the word lines in the second area are disconnected, and the bit lines in the first area and the bit lines in the second area are disconnected. The plurality of VGAA transistors located in the first area form a test array, and a VGAA transistor located in the middle of the test array is a device to be tested.