vGPU Synchronous Rendering via Flag Bits

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Solution Overview

Problem

Current synchronous rendering solutions in virtual graphics processing units (vGPUs) rely on interrupt mechanisms, which occupy significant CPU resources and reduce rendering efficiency due to the high volume of rendering tasks.

Innovation Solution

A method and apparatus for synchronous rendering that utilize synchronization flag bits to manage the generation and rendering of frames without interrupting the virtual machine, thereby reducing CPU resource usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If an interrupt mechanism is used to synchronize rendering between vGPU driver and vGPU, then rendering synchronization reliability is improved, but CPU resource consumption increases

Engineering Contradiction:
Improverendering synchronization reliabilityVSAvoidCPU resource consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent introduces a synchronization flag bit as an intermediary mechanism between the vGPU driver and vGPU. Instead of using CPU interrupts to signal synchronization status, the flag bit acts as a passive indicator that the rendering entity can check at its convenience. This eliminates the need for active interrupt handling while maintaining synchronization reliability, thereby reducing CPU resource consumption.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The rendering entity autonomously checks the synchronization flag bit to determine whether to proceed with rendering operations. This self-service approach replaces the interrupt-driven model where the CPU must actively manage synchronization. The rendering entity serves itself by polling the flag bit and making decisions independently, reducing the burden on CPU resources while ensuring proper synchronization.

Inventive Principle:
Principle #25Self-service

2Measurement precision

If frequent interrupts are triggered for each rendering frame, then synchronization precision is improved, but rendering efficiency deteriorates

Engineering Contradiction:
Improvesynchronization precisionVSAvoidrendering efficiency
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

Instead of continuous interrupt-driven synchronization, the patent implements periodic checking of the synchronization flag bit by the rendering entity. The rendering entity checks the flag bit at regular intervals or at specific checkpoints in the rendering pipeline, maintaining synchronization precision without the overhead of frequent interrupts. This periodic action reduces CPU involvement while ensuring proper coordination between driver and hardware.

Inventive Principle:
Principle #19Periodic action

3Manufacturing precision

If the vGPU driver waits for interrupt completion before generating new rendering commands, then rendering accuracy is improved, but rendering speed decreases

Engineering Contradiction:
Improverendering accuracyVSAvoidrendering speed
Core Design Contradiction:
Manufacturing precisionVSSpeed

Solution Approach 1:

The vGPU driver sets the synchronization flag bit in advance to indicate the status of previous rendering frames before the rendering entity needs to check it. This preliminary action allows the rendering entity to proactively check the flag bit and proceed with command generation as soon as the flag indicates readiness, without waiting for active interrupt completion. This improves rendering speed while maintaining accuracy through the pre-established synchronization signal.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12279063B2Synchronous rendering method, electronic device, and storage medium
Publication Date: 2025.04.15 RUIJIE NETWORK SUZHOU CO LTD
  • US12279063B2 patent drawing
  • US12279063B2 patent drawing
  • US12279063B2 patent drawing

AI summary

This application discloses a synchronous rendering method, a device, and a storage medium. The method includes: determining, by a virtual graphics processing driver based on a second synchronization flag bit of a synchronization signal, whether to generate a rendering frame; after the rendering frame is generated, setting a first synchronization flag bit and the second synchronization flag bit of the synchronization signal to indicate that the rendering frame has been generated; obtaining, by a virtual graphics processing unit, the rendering frame and the synchronization signal, and determining, based on the first synchronization flag bit, whether to render the rendering frame; and after the rendering frame is rendered, setting the first synchronization flag bit and the second synchronization flag bit to indicate that the rendering frame has been rendered.