VHDL Simulation of Embedded Software Requirements for Early Verification
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Solution Overview
Problem
Conventional requirement verification methods for complex embedded systems are inadequate in handling the scale and complexity, leading to potential system failures and high repair costs due to errors or omissions in requirements specification.
Innovation Solution
A VHDL-based semi-automatic simulation method and system that involves pre-defining a domain-specific device model, generating atomic, data storage, and composite controller models, and performing property verification using Vivado to ensure correctness and temporal constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional requirement verification methods are used, then the verification process is simple, but the verification accuracy and comprehensiveness are insufficient for complex embedded systems
Solution Approach 1:
The verification process is segmented into multiple phases: requirement analysis phase, simulation model generation phase, simulation verification phase, and result analysis phase. Each phase handles specific aspects of verification, making the overall complex verification process manageable and systematic. The simulation model itself is segmented into atomic controllers, data storages, and composite controllers that can be verified independently before integration.
Solution Approach 2:
A virtual simulation model is created as a copy of the embedded system using VHDL language. This virtual model replicates the system's structure and behavior, allowing verification without affecting the actual physical system. The simulation model includes virtual versions of controllers, data storages, and devices that can be tested independently and integrated progressively.
2Reliability
If simulation verification is performed early in the development process, then the risk and cost of errors are reduced, but the development time and resources required increase
Solution Approach 1:
Simulation verification is performed preliminarily during the requirement analysis phase before system implementation begins. The simulation model is generated based on requirement specifications, allowing potential errors to be identified and corrected early when the cost of rectification is lowest. This preliminary verification includes generating atomic controller models, data storage models, and composite controller models before final system deployment.
3Measurement precision
If manual construction of device models is performed, then the model accuracy is high, but the time and labor required increase
Solution Approach 1:
The system automatically generates simulation models based on requirement specifications without requiring extensive manual modeling. The model generation process automatically creates atomic controller VHDL models, data storage models, and composite controller models by parsing requirement documents and translating them into verified VHDL code, significantly reducing manual construction time while maintaining accuracy.
4Adaptability or versatility
If comprehensive simulation verification is performed, then the coverage of verification is complete, but the verification cost and complexity increase
Solution Approach 1:
The simulation verification system is designed with universal applicability across different embedded system types. The same VHDL-based framework and verification process can be applied to various systems by simply changing the requirement specifications, without needing system-specific verification tools or methods. The verification platform supports multiple verification scenarios including functional verification, temporal constraint verification, and interaction verification.
Data Source
AI summary
A VHDL-based semi-automatic simulation method and system for software requirements of a complex embedded system are provided, relating to the field of requirements engineering. The method includes: pre-defining a domain-specific device model; generating an atomic controller VHDL model and a data storage VHDL according to atomic controller requirements in a software requirements specification; generating a composite controller VHDL model according to composite controller requirements in the software requirements specification; at a phase of system integration, combining the atomic controller VHDL model, a device VHDL model, the data storage VHDL model and the composite controller VHDL model to obtain a complete system model; at a phase of property verification, performing property verification on the complete system model by using a VHDL verification tool Vivado. VHDL models meeting the requirements can be generated and combined to obtain a complete system model, thereby achieving requirement simulation and property verification.