Via Architecture for High-Density I/O Routing
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Solution Overview
Problem
The packaging size of semiconductor products limits device performance due to restrictions in board layout and density, particularly in mobile devices, where power delivery and input/output routing pose challenges for z-height reduction.
Innovation Solution
The use of self-aligned vias (SAVs) or zero-misaligned vias (ZMVs) and a patterned top metal layer in the package substrate architecture allows for increased I/O routing density by enabling single-ended or differential pair high-speed I/Os to be routed in a single metal layer, with a 1:1 ground-to-signal trace ratio, reducing crosstalk and z-height through closely spaced ground planes and reduced metal layer count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional multi-layer routing structures are used, then signal routing is achieved, but z-height is increased and I/O density is limited
Solution Approach 1:
The patent transitions from traditional multi-layer vertical routing to a single-layer planar routing architecture. By flattening the routing structure into a single metal layer with alternating signal and ground traces, the design eliminates the need for multiple stacked layers, thereby reducing z-height while maintaining routing capacity through increased planar density.
Solution Approach 2:
The patent combines signal routing and ground reference functions into a single metal layer structure. Alternating signal traces and ground traces are integrated in the same layer, eliminating the need for separate ground layers and reducing overall layer count. This merging approach increases routing density while reducing vertical space requirements.
2Object-affected harmful factors
If closely spaced ground planes are implemented, then crosstalk is reduced, but manufacturing complexity increases
Solution Approach 1:
The ground plane is segmented into discrete ground traces that alternate with signal traces in a systematic pattern. Each ground trace is positioned adjacent to signal traces it needs to shield, creating localized shielding zones. This segmentation approach reduces crosstalk by providing nearby ground references without requiring large continuous ground planes, thereby simplifying manufacturing while maintaining electrical performance.
3Productivity
If alternating signal and ground traces are used in a single layer, then I/O density is increased, but trace width and spacing constraints are tightened
Solution Approach 1:
The patent systematically adjusts trace width, spacing, and alternating pattern parameters to optimize the balance between density and manufacturability. By carefully controlling these geometric parameters, the design achieves high I/O density while maintaining adequate clearance for manufacturing processes. The alternating pattern allows for standardized fabrication approaches even as density increases.
Data Source
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AI summary
Aspects of the embodiments are directed to an IC chip that includes a substrate comprising a first metal layer, a second metal layer, and a ground plane residing on the first metal layer. The second metal layer can include a first signal trace, the first signal trace electrically coupled to a first signal pad residing in the first metal layer by a first signal via. The second metal layer can include a second signal trace, the second signal trace electrically coupled to a second signal pad residing in the first metal layer by a second signal via. The substrate can also include a ground trace residing in the second metal layer between the first signal trace and the second signal trace, the ground trace electrically coupled to the ground plane by a ground via. The vias coupled to the traces can include self-aligned or zero-misaligned vias.