Via-Array Alignment Substrate for Universal Component Mounting
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Solution Overview
Problem
The customization of substrate vias for different configurations of external electrical components leads to increased time and cost in development and manufacturing.
Innovation Solution
An electronic device with a via-array substrate and an alignment substrate, featuring varying via densities and alignment mark pads, allowing for universal substrate configurations that eliminate the need for additional alignment mark formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the substrate via arrangement is customized for each external electrical component configuration, then the compatibility with specific components is improved, but the development time and manufacturing cost increase
Solution Approach 1:
The substrate is designed with a universal via array structure that can accommodate multiple different external electrical component configurations. By creating a standardized via distribution pattern with higher density than traditionally used, the same substrate can support various component types and arrangements, eliminating the need for custom via designs for each component configuration.
Solution Approach 2:
The patent pre-establishes a comprehensive via array structure on the substrate before component mounting. This preliminary via configuration, with increased density and specific distribution patterns, anticipates multiple potential component configurations, allowing components to be mounted directly without requiring subsequent via customization or substrate redesign.
2Adaptability or versatility
If the substrate via arrangement is customized for each external electrical component configuration, then the component-specific performance is improved, but the manufacturing cost increases
Solution Approach 1:
A single standardized via array design serves multiple component configurations, reducing the variety of substrate types that need to be manufactured. This universality allows manufacturers to produce larger volumes of identical substrates with optimized via distributions, achieving economies of scale that lower per-unit manufacturing costs compared to producing multiple custom substrate variants.
Solution Approach 2:
The patent employs specific via distribution parameters, particularly higher via density and particular spatial arrangements, that optimize electrical performance across different component configurations. By adjusting these parameters within a standardized framework rather than creating entirely custom designs, the substrate maintains high component-specific performance while using cost-effective manufacturing processes.
3Measurement precision
If alignment marks are formed separately on the substrate, then the alignment precision for component mounting is improved, but the device complexity and manufacturing steps increase
Solution Approach 1:
The alignment mark structure is merged with the existing via array structure on the substrate. By utilizing the same via formation processes and layer structures to create both functional vias and alignment marks, the patent eliminates separate alignment mark formation steps and reduces overall device complexity while maintaining alignment precision.
Solution Approach 2:
The via array structure serves dual purposes: providing electrical connections and providing alignment references for component mounting. The same high-density via pattern that optimizes electrical performance also creates inherent alignment features, allowing the substrate to self-provide alignment functionality without additional dedicated alignment mark structures.
Data Source
AI summary
An electronic device includes a via-array substrate, an outer layer, and an alignment substrate. The via-array substrate has a plurality of first vias. The outer layer has a plurality of second vias and is disposed on a side of the via-array substrate. The first vias are greater in distribution density or quantity than the second vias. A part of the first vias is electrically connected to the second vias, and another part of the first vias is electrically floating. The alignment substrate includes a core layer disposed on the outer layer, a plurality of conductive traces, a plurality of interconnecting pads, and a plurality of alignment mark pads. The conductive traces are disposed in the core layer. The interconnecting pads and the alignment mark pads are disposed on a surface of the core layer located away from the outer layer. A part of the conductive traces electrically connects a part of the interconnecting pads and a part of the first vias. A pattern of each of the alignment mark pads is different from a pattern of each of the interconnecting pads.