Random Via Array Layout with Local Grid Segmentation
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Solution Overview
Problem
As electronic device sizes shrink, there is a challenge in achieving tight packing density due to strong pitch restrictions in integrated circuit (IC) design layouts, particularly in via spacing and arrangement, which is not effectively addressed by existing technologies such as off-axis illumination and immersion lithography, leading to insufficient process margins and higher costs.
Innovation Solution
The method involves placing features on a grid with a local grid area defined by intersecting points, where a first feature is placed on a grid intersecting point, and a second feature can be placed either on a local intersecting point within a pitch restricted area or randomly in a pitch unrestricted area, allowing for increased packing density by defining a plus-shaped outer perimeter of the local grid area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If features are placed on a regular grid with fixed spacing, then manufacturing precision is improved, but packing density deteriorates due to strong pitch restrictions
Solution Approach 1:
The layout space is segmented into multiple grid layers (first grid, second grid, third grid) with different orientations and spacing parameters. Features can be assigned to different grid layers, allowing the design to overcome single-grid pitch restrictions while maintaining manufacturing precision through grid-based placement control.
Solution Approach 2:
The patent transitions from a single two-dimensional grid to a multi-layered grid system where the third dimension (grid layer index) provides additional placement freedom. This dimensional extension allows features to be positioned in pitch-unrestricted areas by selecting appropriate grid layers, thereby increasing packing density without sacrificing precision.
2Measurement precision
If off-axis illumination with sub-resolution assist features is used, then resolution is improved, but manufacturing cost increases
Solution Approach 1:
Instead of using complex optical illumination techniques, the patent creates multiple grid copies (first grid, second grid, third grid) with different orientations and spacing. These grid copies serve as templates for feature placement, achieving resolution and patterning control through geometric design rather than expensive optical modifications.
3Quantity of substance
If features are placed closer together to increase packing density, then quantity of features is improved, but manufacturing precision deteriorates due to pitch restrictions
Solution Approach 1:
The multi-grid system serves multiple functions simultaneously: it provides pitch restriction enforcement through grid-based placement, enables increased packing density through additional placement dimensions, and maintains manufacturing precision through consistent grid spacing parameters. Each grid layer can be configured with appropriate spacing to satisfy different manufacturing requirements.
Data Source
AI summary
Exemplary embodiments provide a method for laying out an integrated circuit (“IC”) design and the IC design layout. In one embodiment, the IC design layout can include a first feature placed on a first intersecting point of a grid. The placed first feature can define a local grid area. The local grid area can further include a plurality of local intersecting points having an outer perimeter spaced from any outermost local intersecting point in a spacing ranging from a length of a grid side to a length of a grid diagonal of a grid unit. A second feature can either be restrictively placed on any local intersecting point of the local grid area, or be randomly placed on any location outside the outer perimeter of the local grid area.