Via Array Merging for Parasitic Extraction Accuracy
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Solution Overview
Problem
Existing parasitic extraction tools for via arrays in electronic design automation (EDA) fail to preserve point-to-point resistance, produce inconsistent results, and create large networks, leading to inaccuracies in post-layout simulation due to non-deterministic merging processes.
Innovation Solution
A system that identifies and merges via arrays by dividing vias into center and end vias, distributing resistance evenly among nodes to maintain point-to-point resistance, ensuring deterministic and consistent extraction results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If existing extraction tools merge all vias in a via array together, then the network size is reduced, but point-to-point resistance is not preserved and accuracy deteriorates
Solution Approach 1:
The patent segments the via array into multiple representative vias (first via, last via, and center via) rather than merging all vias into a single node. This segmentation preserves the spatial distribution and point-to-point resistance characteristics of the original via array while still reducing the network size compared to treating each via as a separate node.
2Device complexity
If existing extraction tools use non-deterministic merging processes, then device complexity is reduced, but result consistency deteriorates
Solution Approach 1:
The patent establishes a predetermined, deterministic merging process where specific vias are selected based on their positions (first, last, and center) before the extraction process begins. This preliminary determination of which vias to merge ensures that the extraction results are consistent and reproducible across different runs, eliminating non-deterministic behavior.
3Quantity of substance
If all vias in a via array are merged into a single node, then the number of nodes is reduced, but the accuracy of parasitic extraction deteriorates
Solution Approach 1:
The patent applies local quality by assigning different roles to different vias based on their positions in the via array. The first via, last via, and center via are treated as representative nodes with specific electrical characteristics, allowing the extraction to capture local variations in parasitic values while still reducing the overall network size.
Data Source
AI summary
Systems and techniques for performing parasitic extraction on a via array are described. If the via array is a single row or column via array, the system identifies a first via and a last via in the via array, and merges a set of vias between the first via and the last via into a center via. If the via array is a M×N (M≧2, N≧2) via array, the system merges the vias as follows: the first row and the last row of vias in the via array into a first row via and a last row via, respectively; the first column and the last column of vias in the via array into a first column via and a last column via, respectively; and a set of vias between the first and last rows and the first and last columns into a center via.