Via Structure for Backside Routing in Micro-Mechanic Devices
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Solution Overview
Problem
Existing micro-mechanic devices face challenges in closely spacing mirrors due to lateral routing of electrical leads, which causes disturbances and requires wire-bonding on the same side of the wafer, limiting further reduction in dimensions and mirror spacing.
Innovation Solution
The use of vias through the wafer to position actuation electrodes underneath mirrors without disturbing other mirrors, allowing for backside routing of leads within the wafer native material, using a layered structure with alternating conductive and insulating layers to provide insulated conductive connections and routing structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If lateral routing of electrical leads is used, then ease of manufacture is improved, but mirror spacing is limited and disturbances to other mirrors occur
Solution Approach 1:
The patent transitions from two-dimensional lateral routing on the wafer surface to three-dimensional routing through vias that penetrate the wafer thickness dimension. Electrical leads are routed through vias from the front surface to the back surface, allowing leads to pass underneath mirrors without occupying lateral space, thereby enabling closer mirror spacing while maintaining manufacturing feasibility.
Solution Approach 2:
The patent embeds electrical leads within the wafer structure itself by creating vias that pass through the substrate. The leads are nested within the wafer thickness, with insulating layers surrounding the conductive leads, effectively hiding the routing within the bulk material rather than occupying surface space.
2Ease of manufacture
If wire-bonding is performed on the same side as mirrors, then electrical connections are achieved, but device dimensions cannot be reduced further
Solution Approach 1:
Instead of making electrical connections on the same side where mirrors are located, the patent inverts the approach by routing leads through the wafer to emerge on the opposite side. This allows the front surface to be dedicated entirely to mirror arrays without competing space requirements for wire-bonding pads and connections.
Solution Approach 2:
The patent utilizes the thickness dimension of the wafer to route electrical connections through vias, separating the connection function from the mirror function in the lateral plane. This vertical routing approach eliminates the need for lateral space dedicated to wire-bonding infrastructure.
3Adaptability or versatility
If electrical leads are routed beneath adjacent mirrors, then actuation of multiple positions is enabled, but disturbance and interference to other mirrors occurs
Solution Approach 1:
The patent introduces insulating layers as intermediary materials surrounding the conductive leads within vias. These insulating enclosures act as barriers that prevent electrical fields from the leads from coupling with or disturbing adjacent mirrors, while still allowing the leads to pass through the wafer to reach actuators on the opposite side.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables closer spacing of mirrors without interference, allows for more compact designs, and facilitates energy harvesting by enabling efficient actuation and routing of electrical signals, improving the operational efficiency of micro-mechanic devices.
Implementation Method 1
an electrically conductive plug extending through the other layers and into said via in the first outer layer in order to provide conductivity through the layers
Data Source
AI summary
A vent hole precursor structure (26) in an intermediate product for a semi-conductor device has delicate structures (27, 28), and said intermediate product has a cavity (21) with a pressure therein differing from the pressure of the surroundings. The intermediate product comprises a first wafer (20) in which there is formed a depression (21). The first wafer is bonded to a second wafer (22) comprising a device layer (23) from which the structures (27, 28) are to be made by etching. A hole or groove (26) having a predefined depth extends downwards into the device layer, such that the cavity (21) during etching is opened up before the etching procedure breaks through the device layer (23) to form the structures (27, 28).