Semiconductor Via Barrier Layer Segmentation for Resistance Reduction
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Solution Overview
Problem
Existing methods for fabricating semiconductor devices face challenges in forming metal interconnections with low resistance, particularly due to high via resistance and process complexity in scaling down IC processing and manufacturing.
Innovation Solution
A method involving a bottom-barrier-free scheme is employed, where a thermal treatment transforms a barrier layer into different materials, and a selective etch is used to remove one portion of the barrier layer, allowing for the deposition of a conductive layer directly over the conductive feature, reducing via resistance and improving device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a barrier layer is formed in via trenches to prevent electron migration, then device reliability is improved, but via resistance increases
Solution Approach 1:
The barrier layer is segmented into two distinct portions: a first portion lining the sidewalls of the via trench and a second portion at the bottom. This segmentation allows the sidewall barrier to prevent electron migration while the bottom barrier is selectively removed to reduce via resistance, resolving the contradiction between reliability and resistance.
Solution Approach 2:
The second portion of the barrier layer at the bottom of the via trench is selectively removed through selective etching. This extraction eliminates the high-resistance barrier material from the via bottom while preserving the sidewall barrier layer that provides electron migration prevention, thus reducing via resistance without compromising device reliability.
2Ease of manufacture
If thermal treatment is applied to transform barrier layer material, then selective etching becomes possible, but process complexity increases
Solution Approach 1:
The barrier layer material is transformed through thermal treatment, changing its physical or chemical parameters. This parameter change enables selective etching by creating material properties that differ between the first and second portions of the barrier layer, allowing selective removal while managing process complexity through controlled thermal processing.
3Productivity
If scaling down is implemented to increase functional density, then production efficiency improves, but manufacturing complexity increases
Solution Approach 1:
The barrier layer is provided with different local qualities: the first portion along the sidewalls maintains full barrier properties for electron migration prevention, while the second portion at the bottom is selectively removed. This local differentiation allows scaling down to increase functional density while managing manufacturing complexity through localized material property variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced via resistance and enhanced device reliability by limiting electron migration and time-dependent dielectric breakdown, while simplifying the manufacturing process and improving interconnection formation.
Implementation Method 1
applying a thermal treatment to convert the first portion of the barrier layer to a second barrier layer
Implementation Method 2
a selective etch is used to remove one portion of the barrier layer
Data Source
AI summary
A method of fabricating a semiconductor device is disclosed. The method includes forming a first conductive feature over a substrate, forming a dielectric layer over the first conductive feature, forming a via trench in the dielectric layer, forming a first barrier layer in the via trench. Therefore the first barrier has a first portion disposed over the dielectric layer and a second portion disposed over the first conductive feature, applying a thermal treatment to convert the first portion of the barrier layer to a second barrier layer and exposing the first conductive feature in the via trench while a portion of the second barrier layer is disposed over the dielectric layer.