Via Bottom Barrier Layer for Copper Diffusion Reliability
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Solution Overview
Problem
In semiconductor device manufacturing, previous approaches to applying barrier layers along the bottom surfaces of vias result in diffusion into the metal layer below, affecting the reliability of the device due to high temperatures used.
Innovation Solution
A method involving selectively applying a barrier layer, such as cobalt or tantalum, only to the bottom surface of a via, followed by a liner layer on the sidewalls, and filling the via with a metal layer, while processing to remove the liner layer and maintain the barrier layer's integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a barrier layer is applied along multiple surfaces of a via including the bottom surface, then electrical conductivity between layers is provided, but the barrier layer diffuses into the metal layer below during high temperature processing, adversely impacting device reliability
Solution Approach 1:
The barrier layer application is segmented to cover only specific surfaces of the via (sidewalls and bottom), excluding the top surface. This selective segmentation prevents diffusion into the underlying metal layer while maintaining barrier functionality where needed, resolving the contradiction between providing electrical conductivity and preventing harmful diffusion during high temperature processing.
Solution Approach 2:
The barrier layer is applied with local quality differentiation - present on sidewalls and bottom surfaces where barrier functionality is required, but absent from the top surface where it would cause harmful diffusion. This localized application strategy maintains device reliability by preventing composition instability in the metal layer below while still providing necessary electrical isolation elsewhere.
2Productivity
If high temperatures are used during device processing, then manufacturing processes can be completed, but the barrier layer positioned along the bottom surface of the via diffuses into the metal layer
Solution Approach 1:
By segmenting the barrier layer coverage to exclude the top surface of the via, the invention enables high temperature processing to proceed without causing barrier layer diffusion into the metal layer. This segmentation allows manufacturing efficiency to be maintained through standard high temperature processes while preventing reliability degradation from unwanted diffusion.
3Reliability
If the barrier layer is applied to the bottom surface of the via, then electrical isolation is provided, but diffusion into the metal layer occurs during subsequent processing
Solution Approach 1:
The barrier layer is segmented to cover the bottom surface and sidewalls where electrical isolation is needed, but deliberately excludes the top surface to prevent diffusion into the metal layer. This selective segmentation maintains electrical isolation effectiveness while eliminating the harmful diffusion effect that occurs when the barrier layer is applied to all surfaces including the top.
Solution Approach 2:
The barrier layer exhibits local quality by being present only where electrical isolation is required (bottom and sidewalls) and absent where it would create harmful effects (top surface). This localized application resolves the contradiction between maintaining electrical isolation effectiveness and preventing diffusion-generated harmful factors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents diffusion and enhances the reliability of semiconductor devices by isolating the barrier layer from the metal layer, maintaining its effectiveness without adverse thermal impacts.
Implementation Method 1
a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier is selectively applied to a bottom surface of the via
Implementation Method 2
annealing the semiconductor device
Data Source
AI summary
An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier) is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may the then be further processed (e.g., annealed).