Via Structure With Enlarged Bottom Footing for Low-Resistance Contacts
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Solution Overview
Problem
Conventional via formation methods in semiconductor fabrication result in increased electrical resistance and the risk of open circuits due to the reduced cross-sectional area at the bottom of vias, which can impact production yield and interconnect reliability.
Innovation Solution
The formation of vias with an enlarged bottom footing profile, achieved through a method involving anisotropic and isotropic etching processes, ensures a larger cross-sectional area at the bottom, reducing resistance and enhancing bonding with lower metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional via formation methods are used, then via structure is simple to manufacture, but electrical resistance increases and reliability deteriorates due to reduced cross-sectional area at via bottom
Solution Approach 1:
The via formation process is divided into multiple etching stages: a first etching process creates an initial via structure, and a second etching process enlarges the via bottom footing. This segmentation allows each process to be optimized independently, achieving both manufacturing feasibility and improved via reliability through enlarged cross-sectional area at the bottom.
Solution Approach 2:
The first etching process performs preliminary via structure formation with controlled depth and profile, preparing the structure for the second etching process that will enlarge the bottom footing. This preliminary action ensures that the subsequent enlargement process can be precisely controlled to achieve the desired cross-sectional area increase without compromising overall via integrity.
2Productivity
If via size is scaled down to match component scaling, then integration density increases, but via cross-sectional area decreases causing increased resistance and open circuit risk
Solution Approach 1:
The via structure is designed with non-uniform cross-sectional area along its length, creating a localized enlargement at the bottom footing while maintaining smaller dimensions at the top. This local quality change increases the cross-sectional area specifically where it is most needed for current carrying and mechanical support, thereby improving reliability without increasing overall via footprint and maintaining integration density.
Solution Approach 2:
Instead of uniformly scaling via dimensions in all directions, the invention modifies the via geometry in the vertical dimension by creating an enlarged bottom footing. This dimensional modification increases the cross-sectional area at the critical bottom region while maintaining the via's overall small footprint, thus improving electrical connection reliability without compromising integration density.
3Productivity
If via cross-sectional area is reduced for scaling, then more vias can fit on chip, but electrical resistance increases due to smaller conductive area
Solution Approach 1:
The via structure concentrates the cross-sectional area enlargement at the bottom footing where current density is highest, rather than uniformly increasing the via dimensions. This local quality improvement reduces electrical resistance at the critical current flow path while maintaining the via's small overall size, thus reducing energy loss without decreasing via density on the chip.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces electrical resistance and strengthens the bonding of conductive features, minimizing the risk of open circuits and improving the overall reliability and efficiency of semiconductor devices.
Implementation Method 1
a first portion of the via hole is etched into the low-k dielectric layer
Implementation Method 2
a second portion of the via hole is etched into the etch stop layer such that a cross-sectional area of a lower portion of the via hole is larger than a smallest cross-sectional area of the upper portion of the via hole
Data Source
AI summary
A semiconductor device includes a substrate, a bottom etch stop layer over the substrate, a middle etch stop layer over the bottom etch stop layer, and a top etch stop layer over the middle etch stop layer. The top, middle, and bottom etch stop layers include different material compositions from each other. The semiconductor device further includes a dielectric layer over the top etch stop layer and a via extending through the dielectric layer and the top, middle, and bottom etch stop layers. The via has a first sidewall in contact with the dielectric layer and slanted inwardly from top to bottom towards a center of the via and a second sidewall in contact with the bottom etch stop layer and slanted outwardly from top to bottom away from the center of the via.