Via-Integrated Capacitors for mmWave IC Power Decoupling
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Solution Overview
Problem
Existing capacitors in integrated circuits (ICs) fail to provide sufficient decoupling capacitance at millimeter wave (mmWave) frequencies, leading to high power delivery network impedance and unstable power delivery due to degraded quality factors and non-linear capacitance scaling with finger structures, which complicates design and increases costs with additional trimming circuits.
Innovation Solution
The implementation of capacitors in opened vias between adjacent metal layers using a high dielectric constant material to increase capacitance by reducing the distance and enhancing the surface area between metal electrodes, while maintaining electrical isolation, allowing for decoupling from standard BEOL processes and enabling linear scaling of capacitance without design overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional finger capacitors are used in integrated circuits, then the capacitor structure is simple to fabricate, but the decoupling capacitance is insufficient at mmWave frequencies due to degraded quality factors and non-linear capacitance scaling
Solution Approach 1:
The patent transitions from planar finger capacitor structures to three-dimensional capacitor implementations utilizing vertical vias and stacked metal layers. This dimensional change enables significantly higher capacitance density by exploiting the vertical dimension, allowing capacitors to provide sufficient decoupling capacitance at mmWave frequencies without requiring excessive lateral space or complex trimming circuits
Solution Approach 2:
The patent employs composite material structures combining multiple dielectric layers with different properties (e.g., high-k dielectric materials mixed with low-k materials) and various conductive materials in the via structures. This composite approach optimizes both the capacitance value and the quality factor at mmWave frequencies while maintaining manufacturability through standard BEOL processes
2Reliability
If finger structures are used to increase capacitance, then the capacitance value increases, but the scaling becomes non-linear requiring additional trimming circuits that complicate design and increase costs
Solution Approach 1:
By moving to vertical via-based capacitor structures, the patent achieves linear scaling of capacitance with the number of via structures. Each via contributes a predictable, consistent capacitance value, allowing designers to simply add or remove via structures to achieve desired capacitance values without requiring non-linear compensation or trimming circuits
Solution Approach 2:
The patent divides the total capacitance requirement into multiple discrete, identical via capacitor units. Each via structure is a standardized segment with consistent electrical characteristics, enabling modular design where capacitance is scaled linearly by repeating the basic via unit rather than adjusting complex finger structure geometries
3Reliability
If capacitor size is increased to provide sufficient decoupling capacitance, then the capacitance value improves, but the integration density decreases
Solution Approach 1:
The patent exploits the vertical dimension by stacking capacitor structures across multiple metal layers and utilizing deep via structures. This enables high capacitance values to be achieved within a small lateral footprint, as the capacitance accumulates in the vertical direction rather than requiring large planar areas, thereby maintaining high integration density
Solution Approach 2:
The patent implements nested capacitor structures where capacitor elements are embedded within the interconnect stack, utilizing the space between existing metal layers and via structures. This nesting approach allows capacitors to share space with the interconnect architecture, achieving high capacitance without dedicating separate large areas solely to capacitor functions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances capacitance in IC devices, reduces parasitic capacitance, and improves integration density, enabling stable power delivery and efficient operation at mmWave frequencies without the need for additional trimming circuits, thus simplifying design and reducing costs.
Implementation Method 1
The implementation of capacitors in opened vias between adjacent metal layers using a high dielectric constant material to increase capacitance by reducing the distance and enhancing the surface area between metal electrodes
Data Source
AI summary
Methods and apparatus are disclosed for implementing capacitors in semiconductor devices. An example semiconductor die includes a first dielectric material disposed between a first metal interconnect and a second metal interconnect; and a capacitor positioned within a via extending through the first dielectric material between the first and second metal interconnects, the capacitor including a second dielectric material disposed in the via between the first and second metal interconnects.